RISC-V: Fix riscv g++ testsuite EH failures.

This fixes some EH failures for the medany code model in the g++ testsuite.
The problem is that the assembler is computing some values in the eh_frame
section as constants, that instead should have had relocs to be resolved by
the linker.  This happens in output_cfi_insn in the DW_CFA_advance_loc case
where it compares label frags and immediately simplifies if they are the
same.  We can fix that by forcing a new frag after every instruction
that the linker can reduce in size.  I've also added a testcase to verify
the fix.  This was tested with binutils make check, and gcc/g++ make checks on
qemu for medlow and medany code models.

	gas/
	* config/tc-riscv.c (append_insn): Call frag_wane and frag_new at
	end for linker optimizable relocs.
	* testsuite/gas/riscv/eh-relocs.d: New.
	* testsuite/gas/riscv/eh-relocs.s: New.
	* testsuite/gas/riscv/riscv.exp: Run eh-relocs test.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 85f0664a6d78f4d77ddb461213cefd6cf5b45b38..80e9ea751cf3cbec8ec03a31d9e49e98810a019b 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,11 @@
+2017-11-07  Jim Wilson  <jimw@sifive.com>
+
+       * config/tc-riscv.c (append_insn): Call frag_wane and frag_new at
+       end for linker optimizable relocs.
+       * testsuite/gas/riscv/eh-relocs.d: New.
+       * testsuite/gas/riscv/eh-relocs.s: New.
+       * testsuite/gas/riscv/riscv.exp: Run eh-relocs test.
+
 2017-11-07  Palmer Dabbelt  <palmer@dabbelt.com>
 
        * testsuite/gas/riscv/satp.d: New test.

diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index c8955a69ecd1f9bf733c2f1fa0f3e494fa017752..bdaf270470aca95d631345a29cbab182859960e1 100644 (file)
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -716,6 +716,21 @@ append_insn (struct riscv_cl_insn *ip, expressionS *address_expr,
 
   add_fixed_insn (ip);
   install_insn (ip);
+
+  /* We need to start a new frag after any instruction that can be
+     optimized away or compressed by the linker during relaxation, to prevent
+     the assembler from computing static offsets across such an instruction.
+     This is necessary to get correct EH info.  */
+  if (reloc_type == BFD_RELOC_RISCV_CALL
+      || reloc_type == BFD_RELOC_RISCV_CALL_PLT
+      || reloc_type == BFD_RELOC_RISCV_HI20
+      || reloc_type == BFD_RELOC_RISCV_PCREL_HI20
+      || reloc_type == BFD_RELOC_RISCV_TPREL_HI20
+      || reloc_type == BFD_RELOC_RISCV_TPREL_ADD)
+    {
+      frag_wane (frag_now);
+      frag_new (0);
+    }
 }
 
 /* Build an instruction created by a macro expansion.  This is passed

diff --git a/gas/testsuite/gas/riscv/eh-relocs.d b/gas/testsuite/gas/riscv/eh-relocs.d
new file mode 100644 (file)
index 0000000..94fa143
--- /dev/null
+++ b/gas/testsuite/gas/riscv/eh-relocs.d
@@ -0,0 +1,12 @@
+#as:
+#objdump: --section=.eh_frame -r
+
+.*:[   ]+file format .*
+
+RELOCATION RECORDS FOR .*
+.*
+0+1c R_RISCV_32_PCREL.*
+0+20 R_RISCV_ADD32.*
+0+20 R_RISCV_SUB32.*
+0+25 R_RISCV_SET6.*
+0+25 R_RISCV_SUB6.*

diff --git a/gas/testsuite/gas/riscv/eh-relocs.s b/gas/testsuite/gas/riscv/eh-relocs.s
new file mode 100644 (file)
index 0000000..4e96e7e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/eh-relocs.s
@@ -0,0 +1,11 @@
+       .text
+       .align  2
+       .globl  _func1
+       .type   _func1, @function
+_func1:
+       .cfi_startproc
+       lla     a1,_func2
+       add     sp,sp,-16
+       .cfi_def_cfa_offset 16
+       .cfi_endproc
+       .size   _func1, .-_func1

diff --git a/gas/testsuite/gas/riscv/riscv.exp b/gas/testsuite/gas/riscv/riscv.exp
index 2ab885ad87a1b6eb7b2a3f2b89a750b4b76d3a0d..8a128acdcf097b91683b3ebee2cea903576d8674 100644 (file)
--- a/gas/testsuite/gas/riscv/riscv.exp
+++ b/gas/testsuite/gas/riscv/riscv.exp
@@ -25,4 +25,5 @@ if [istarget riscv*-*-*] {
     run_dump_test "c-addi4spn-fail"
     run_dump_test "c-addi16sp-fail"
     run_dump_test "satp"
+    run_dump_test "eh-relocs"
 }