--- /dev/null
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=DerivO3CPU
+children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+cachePorts=200
+checker=Null
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+cpu_id=0
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+defer_registration=false
+dispatchWidth=8
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+issueToExecuteDelay=1
+issueWidth=8
+itb=system.cpu.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+phase=0
+predType=tournament
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+squashWidth=8
+system=system
+tracer=system.cpu.tracer
+trapLatency=13
+wbDepth=1
+wbWidth=8
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=ArmTLB
+size=64
+
+[system.cpu.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+children=opList
+count=6
+opList=system.cpu.fuPool.FUList0.opList
+
+[system.cpu.fuPool.FUList0.opList]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntMult
+opLat=3
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+issueLat=19
+opClass=IntDiv
+opLat=20
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList4.opList
+
+[system.cpu.fuPool.FUList4.opList]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
+count=4
+opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+
+[system.cpu.fuPool.FUList5.opList00]
+type=OpDesc
+issueLat=1
+opClass=SimdAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList01]
+type=OpDesc
+issueLat=1
+opClass=SimdAddAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList02]
+type=OpDesc
+issueLat=1
+opClass=SimdAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList03]
+type=OpDesc
+issueLat=1
+opClass=SimdCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList04]
+type=OpDesc
+issueLat=1
+opClass=SimdCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList05]
+type=OpDesc
+issueLat=1
+opClass=SimdMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList06]
+type=OpDesc
+issueLat=1
+opClass=SimdMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList07]
+type=OpDesc
+issueLat=1
+opClass=SimdMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList08]
+type=OpDesc
+issueLat=1
+opClass=SimdShift
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList09]
+type=OpDesc
+issueLat=1
+opClass=SimdShiftAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList10]
+type=OpDesc
+issueLat=1
+opClass=SimdSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList11]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList12]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList13]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList14]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList15]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatDiv
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList16]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList17]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList18]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList19]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList6.opList
+
+[system.cpu.fuPool.FUList6.opList]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList7.opList1]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList8]
+type=FUDesc
+children=opList
+count=1
+opList=system.cpu.fuPool.FUList8.opList
+
+[system.cpu.fuPool.FUList8.opList]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=ArmTLB
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=gzip input.log 1
+cwd=build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/gzip
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[0]
+
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+hack: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jan 11 2011 18:16:01
+M5 revision b39a8457b332 7816 default ext/o3_regressions.patch qtip tip
+M5 started Jan 12 2011 02:01:01
+M5 executing on u200439-lin.austin.arm.com
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+spec_init
+Loading Input Data
+Duplicating 262144 bytes
+Duplicating 524288 bytes
+Input data 1048576 bytes in length
+Compressing Input Data, level 1
+Compressed data 108074 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 3
+Compressed data 97831 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 5
+Compressed data 83382 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 7
+Compressed data 76606 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 73189 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
+Exiting @ tick 216988313500 because target called exit()
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 117336 # Simulator instruction rate (inst/s)
+host_mem_usage 251760 # Number of bytes of host memory used
+host_seconds 5118.46 # Real time elapsed on the host
+host_tick_rate 42393313 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 600581394 # Number of instructions simulated
+sim_seconds 0.216988 # Number of seconds simulated
+sim_ticks 216988313500 # Number of ticks simulated
+system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.BTBHits 80605282 # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 86770000 # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect 3926724 # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted 92457745 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 92457745 # Number of BP lookups
+system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
+system.cpu.commit.COM:branches 70067581 # Number of branches committed
+system.cpu.commit.COM:bw_lim_events 7237695 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
+system.cpu.commit.COM:committed_per_cycle::samples 415629341 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean 1.444993 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev 1.803103 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0 151329728 36.41% 36.41% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1 131463070 31.63% 68.04% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2 59591076 14.34% 82.38% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3 19300079 4.64% 87.02% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4 16801344 4.04% 91.06% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5 14774924 3.55% 94.62% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6 12865596 3.10% 97.71% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7 2265829 0.55% 98.26% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8 7237695 1.74% 100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total 415629341 # Number of insts commited each cycle
+system.cpu.commit.COM:count 600581394 # Number of instructions committed
+system.cpu.commit.COM:loads 148953025 # Number of loads committed
+system.cpu.commit.COM:membars 0 # Number of memory barriers committed
+system.cpu.commit.COM:refs 219174038 # Number of memory references committed
+system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
+system.cpu.commit.branchMispredicts 4754911 # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 600581394 # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls 3642 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts 121350527 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 600581394 # Number of Instructions Simulated
+system.cpu.committedInsts_total 600581394 # Number of Instructions Simulated
+system.cpu.cpi 0.722594 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.722594 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 140357692 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 13127.051417 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7797.439109 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 140121331 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 3102723000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.001684 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 236361 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 40726 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 1525452000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.001394 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 195635 # number of ReadReq MSHR misses
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+system.cpu.dcache.WriteReq_avg_miss_latency 17787.356145 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10360.258061 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 67933393 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 26422494996 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.021399 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 1485465 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 1237601 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 2567935004 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.003571 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 247864 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 4386.427788 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 469.123189 # Average number of references to valid blocks.
+system.cpu.dcache.blocked::no_mshrs 2188 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs 9597504 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 209776550 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 17147.620024 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 9229.754755 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 208054724 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 29525217996 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.008208 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 1721826 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 1278327 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 4093387004 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.002114 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 443499 # number of demand (read+write) MSHR misses
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+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0 0.999739 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 4094.932542 # Average occupied blocks per context
+system.cpu.dcache.overall_accesses 209776550 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 17147.620024 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 9229.754755 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 208054724 # number of overall hits
+system.cpu.dcache.overall_miss_latency 29525217996 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.008208 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 1721826 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 1278327 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 4093387004 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.002114 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 443499 # number of overall MSHR misses
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+system.cpu.dcache.replacements 439401 # number of replacements
+system.cpu.dcache.sampled_refs 443497 # Sample count of references to valid blocks.
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+system.cpu.dcache.tagsinuse 4094.932542 # Cycle average of tags in use
+system.cpu.dcache.total_refs 208054727 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 90722000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 394050 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 84141891 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:DecodedInsts 763382279 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 172756991 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 145179524 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 17468389 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:UnblockCycles 13550935 # Number of cycles decode is unblocking
+system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.inst_hits 0 # ITB inst hits
+system.cpu.dtb.inst_misses 0 # ITB inst misses
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.read_hits 0 # DTB read hits
+system.cpu.dtb.read_misses 0 # DTB read misses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.write_hits 0 # DTB write hits
+system.cpu.dtb.write_misses 0 # DTB write misses
+system.cpu.fetch.Branches 92457745 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 75163464 # Number of cache lines fetched
+system.cpu.fetch.Cycles 161721844 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 803289 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 727645117 # Number of instructions fetch has processed
+system.cpu.fetch.MiscStallCycles 2728 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.SquashCycles 5447650 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.213048 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 75163464 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 80605282 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 1.676692 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples 433097730 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.793885 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.871524 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 271377208 62.66% 62.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 26620227 6.15% 68.81% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 18536414 4.28% 73.09% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 23464508 5.42% 78.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 11465886 2.65% 81.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 12676535 2.93% 84.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 5122175 1.18% 85.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 7816549 1.80% 87.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 56018228 12.93% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 433097730 # Number of instructions fetched each cycle (Total)
+system.cpu.icache.ReadReq_accesses 75163464 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 35391.803279 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 34026.104418 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 75162549 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 32383500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000012 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 915 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 168 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 25417500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 747 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 100889.327517 # Average number of references to valid blocks.
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 75163464 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 35391.803279 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 34026.104418 # average overall mshr miss latency
+system.cpu.icache.demand_hits 75162549 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 32383500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000012 # miss rate for demand accesses
+system.cpu.icache.demand_misses 915 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 168 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 25417500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000010 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 747 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0 0.323287 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 662.091545 # Average occupied blocks per context
+system.cpu.icache.overall_accesses 75163464 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 35391.803279 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 34026.104418 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 75162549 # number of overall hits
+system.cpu.icache.overall_miss_latency 32383500 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000012 # miss rate for overall accesses
+system.cpu.icache.overall_misses 915 # number of overall misses
+system.cpu.icache.overall_mshr_hits 168 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 25417500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000010 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 747 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.replacements 23 # number of replacements
+system.cpu.icache.sampled_refs 745 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 662.091545 # Cycle average of tags in use
+system.cpu.icache.total_refs 75162549 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idleCycles 878898 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 74261584 # Number of branches executed
+system.cpu.iew.EXEC:nop 0 # number of nop insts executed
+system.cpu.iew.EXEC:rate 1.487821 # Inst execution rate
+system.cpu.iew.EXEC:refs 240772759 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 74373435 # Number of stores executed
+system.cpu.iew.EXEC:swp 0 # number of swp insts executed
+system.cpu.iew.WB:consumers 747728848 # num instructions consuming a value
+system.cpu.iew.WB:count 638555092 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.593985 # average fanout of values written-back
+system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.WB:producers 444140092 # num instructions producing a value
+system.cpu.iew.WB:rate 1.471404 # insts written-back per cycle
+system.cpu.iew.WB:sent 640268738 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 5263099 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 938806 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 184696678 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 3886 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 3056895 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 88578802 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 721929575 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 166399324 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 7744433 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 645679694 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 15541 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu.iew.iewLSQFullEvents 10568 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 17468389 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 68840 # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked 8986 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 24659910 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 40290 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.memOrderViolation 927620 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 15164 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 35743652 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 18357789 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 927620 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 1456086 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 3807013 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 1.383903 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.383903 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntAlu 408584049 62.53% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntMult 6689 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 3 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemRead 168909832 25.85% 88.38% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemWrite 75923554 11.62% 100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::total 653424127 # Type of FU issued
+system.cpu.iq.ISSUE:fu_busy_cnt 7689778 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.011768 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntAlu 110226 1.43% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemRead 7362915 95.75% 97.18% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemWrite 216637 2.82% 100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:issued_per_cycle::samples 433097730 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::mean 1.508722 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.485636 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0 131709381 30.41% 30.41% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1 125173843 28.90% 59.31% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2 78416744 18.11% 77.42% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3 46404818 10.71% 88.13% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4 32896297 7.60% 95.73% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5 12946022 2.99% 98.72% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6 3892650 0.90% 99.62% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7 732656 0.17% 99.79% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::8 925319 0.21% 100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::total 433097730 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate 1.505667 # Inst issue rate
+system.cpu.iq.iqInstsAdded 721925689 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 653424127 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 3886 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 120964345 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 625992 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 244 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 239956902 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.inst_hits 0 # ITB inst hits
+system.cpu.itb.inst_misses 0 # ITB inst misses
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.l2cache.ReadExReq_accesses 247865 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34472.327689 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31273.618950 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_hits 189395 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency 2015597000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 0.235895 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 58470 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 1828568500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235895 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 58470 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 196377 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34258.171034 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31117.674945 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 163670 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 1120482000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.166552 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 32707 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_miss_latency 1017423500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.166496 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 32696 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 394050 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 394050 # number of Writeback hits
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs 6190.332326 # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 4.731748 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked::no_mshrs 331 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_mshrs 2049000 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 444242 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34395.505445 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31217.690806 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 353065 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 3136079000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.205242 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 91177 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 11 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 2845992000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.205217 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 91166 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0 0.056947 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.488639 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 1866.034390 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 16011.711399 # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses 444242 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34395.505445 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31217.690806 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 353065 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 3136079000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.205242 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 91177 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 11 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 2845992000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.205217 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 91166 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.replacements 72987 # number of replacements
+system.cpu.l2cache.sampled_refs 88484 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 17877.745789 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 418684 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 58152 # number of writebacks
+system.cpu.memDep0.conflictingLoads 56143840 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 33466008 # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads 184696678 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 88578802 # Number of stores inserted to the mem dependence unit.
+system.cpu.numCycles 433976628 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 12394432 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps 469246940 # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents 63310884 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 190432951 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 3181742 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents 1 # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups 2146132338 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 749362118 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 579635257 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 140765492 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 17468389 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 71980169 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 110388314 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 56297 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 3959 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 128598467 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 3953 # count of temporary serializing insts renamed
+system.cpu.timesIdled 36486 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.workload.PROG:num_syscalls 48 # Number of system calls
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=DerivO3CPU
+children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+cachePorts=200
+checker=Null
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+cpu_id=0
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+defer_registration=false
+dispatchWidth=8
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+fetchToDecodeDelay=1
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+forwardComSize=5
+fuPool=system.cpu.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
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+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+issueToExecuteDelay=1
+issueWidth=8
+itb=system.cpu.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+phase=0
+predType=tournament
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+squashWidth=8
+system=system
+tracer=system.cpu.tracer
+trapLatency=13
+wbDepth=1
+wbWidth=8
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=ArmTLB
+size=64
+
+[system.cpu.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+children=opList
+count=6
+opList=system.cpu.fuPool.FUList0.opList
+
+[system.cpu.fuPool.FUList0.opList]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntMult
+opLat=3
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+issueLat=19
+opClass=IntDiv
+opLat=20
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList4.opList
+
+[system.cpu.fuPool.FUList4.opList]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
+count=4
+opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+
+[system.cpu.fuPool.FUList5.opList00]
+type=OpDesc
+issueLat=1
+opClass=SimdAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList01]
+type=OpDesc
+issueLat=1
+opClass=SimdAddAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList02]
+type=OpDesc
+issueLat=1
+opClass=SimdAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList03]
+type=OpDesc
+issueLat=1
+opClass=SimdCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList04]
+type=OpDesc
+issueLat=1
+opClass=SimdCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList05]
+type=OpDesc
+issueLat=1
+opClass=SimdMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList06]
+type=OpDesc
+issueLat=1
+opClass=SimdMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList07]
+type=OpDesc
+issueLat=1
+opClass=SimdMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList08]
+type=OpDesc
+issueLat=1
+opClass=SimdShift
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList09]
+type=OpDesc
+issueLat=1
+opClass=SimdShiftAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList10]
+type=OpDesc
+issueLat=1
+opClass=SimdSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList11]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList12]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList13]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList14]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList15]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatDiv
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList16]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList17]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList18]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList19]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList6.opList
+
+[system.cpu.fuPool.FUList6.opList]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList7.opList1]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList8]
+type=FUDesc
+children=opList
+count=1
+opList=system.cpu.fuPool.FUList8.opList
+
+[system.cpu.fuPool.FUList8.opList]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=ArmTLB
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=mcf mcf.in
+cwd=build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/mcf
+gid=100
+input=/chips/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=55300000000
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:268435455
+zero=false
+port=system.membus.port[0]
+
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
+hack: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jan 11 2011 18:16:01
+M5 revision b39a8457b332 7816 default ext/o3_regressions.patch qtip tip
+M5 started Jan 12 2011 03:03:04
+M5 executing on u200439-lin.austin.arm.com
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+
+MCF SPEC version 1.6.I
+by Andreas Loebel
+Copyright (c) 1998,1999 ZIB Berlin
+All Rights Reserved.
+
+nodes : 500
+active arcs : 1905
+simplex iterations : 1502
+flow value : 4990014995
+new implicit arcs : 23867
+active arcs : 25772
+simplex iterations : 2663
+flow value : 3080014995
+checksum : 68389
+optimal
+Exiting @ tick 56054650500 because target called exit()
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 109166 # Simulator instruction rate (inst/s)
+host_mem_usage 384348 # Number of bytes of host memory used
+host_seconds 835.45 # Real time elapsed on the host
+host_tick_rate 67095197 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 91202735 # Number of instructions simulated
+sim_seconds 0.056055 # Number of seconds simulated
+sim_ticks 56054650500 # Number of ticks simulated
+system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.BTBHits 20717891 # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 22133087 # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect 1885128 # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted 22369136 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 22369136 # Number of BP lookups
+system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
+system.cpu.commit.COM:branches 18672384 # Number of branches committed
+system.cpu.commit.COM:bw_lim_events 365812 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
+system.cpu.commit.COM:committed_per_cycle::samples 109380669 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean 0.833810 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev 1.220278 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0 55493598 50.73% 50.73% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1 34988156 31.99% 82.72% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2 8951301 8.18% 90.91% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3 6346851 5.80% 96.71% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4 1763725 1.61% 98.32% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5 198423 0.18% 98.50% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6 611708 0.56% 99.06% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7 661095 0.60% 99.67% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8 365812 0.33% 100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total 109380669 # Number of insts commited each cycle
+system.cpu.commit.COM:count 91202735 # Number of instructions committed
+system.cpu.commit.COM:loads 22585492 # Number of loads committed
+system.cpu.commit.COM:membars 0 # Number of memory barriers committed
+system.cpu.commit.COM:refs 27330336 # Number of memory references committed
+system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
+system.cpu.commit.branchMispredicts 1941616 # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 91202735 # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls 544722 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts 11836568 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 91202735 # Number of Instructions Simulated
+system.cpu.committedInsts_total 91202735 # Number of Instructions Simulated
+system.cpu.cpi 1.229232 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.229232 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 23356359 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 5257.244166 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2204.745551 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 22405801 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 4997315500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.040698 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 950558 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 47017 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 1992078000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.038685 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 903541 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 4738868 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 21505.165872 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20098.081505 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 4602377 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 2935261595 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.028802 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 136491 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 89917 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 936048048 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.009828 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 46574 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 2906.794309 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 28.426220 # Average number of references to valid blocks.
+system.cpu.dcache.blocked::no_mshrs 6009 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs 17466927 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 28095227 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 7297.350069 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 3081.864877 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 27008178 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 7932577095 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.038692 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 1087049 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 136934 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 2928126048 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.033818 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 950115 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0 0.851200 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 3486.513521 # Average occupied blocks per context
+system.cpu.dcache.overall_accesses 28095227 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 7297.350069 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 3081.864877 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 27008178 # number of overall hits
+system.cpu.dcache.overall_miss_latency 7932577095 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.038692 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 1087049 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 136934 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 2928126048 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.033818 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 950115 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.replacements 946019 # number of replacements
+system.cpu.dcache.sampled_refs 950115 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 3486.513521 # Cycle average of tags in use
+system.cpu.dcache.total_refs 27008178 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 23888323000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 943195 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 6646244 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:DecodedInsts 108354442 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 27877026 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 74250528 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 2697133 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:UnblockCycles 606871 # Number of cycles decode is unblocking
+system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.inst_hits 0 # ITB inst hits
+system.cpu.dtb.inst_misses 0 # ITB inst misses
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.read_hits 0 # DTB read hits
+system.cpu.dtb.read_misses 0 # DTB read misses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.write_hits 0 # DTB write hits
+system.cpu.dtb.write_misses 0 # DTB write misses
+system.cpu.fetch.Branches 22369136 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 12683523 # Number of cache lines fetched
+system.cpu.fetch.Cycles 76804790 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 214313 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 109645009 # Number of instructions fetch has processed
+system.cpu.fetch.MiscStallCycles 18268 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.SquashCycles 1945737 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.199530 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 12683523 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 20717891 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 0.978019 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples 112077802 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.986563 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 1.108840 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 35656336 31.81% 31.81% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 60887091 54.33% 86.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 7618220 6.80% 92.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 828250 0.74% 93.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 4141724 3.70% 97.37% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 2560072 2.28% 99.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 241811 0.22% 99.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 9014 0.01% 99.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 135284 0.12% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 112077802 # Number of instructions fetched each cycle (Total)
+system.cpu.icache.ReadReq_accesses 12683523 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 36326.451613 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 34504.457652 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 12682748 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 28153000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000061 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 775 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 102 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 23221500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000053 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 673 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 18845.093611 # Average number of references to valid blocks.
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 12683523 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 36326.451613 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 34504.457652 # average overall mshr miss latency
+system.cpu.icache.demand_hits 12682748 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 28153000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000061 # miss rate for demand accesses
+system.cpu.icache.demand_misses 775 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 102 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 23221500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000053 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 673 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0 0.278329 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 570.018362 # Average occupied blocks per context
+system.cpu.icache.overall_accesses 12683523 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 36326.451613 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 34504.457652 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 12682748 # number of overall hits
+system.cpu.icache.overall_miss_latency 28153000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000061 # miss rate for overall accesses
+system.cpu.icache.overall_misses 775 # number of overall misses
+system.cpu.icache.overall_mshr_hits 102 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 23221500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000053 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 673 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.replacements 3 # number of replacements
+system.cpu.icache.sampled_refs 673 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 570.018362 # Cycle average of tags in use
+system.cpu.icache.total_refs 12682748 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idleCycles 31500 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 19532471 # Number of branches executed
+system.cpu.iew.EXEC:nop 0 # number of nop insts executed
+system.cpu.iew.EXEC:rate 0.868515 # Inst execution rate
+system.cpu.iew.EXEC:refs 28649530 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 5007242 # Number of stores executed
+system.cpu.iew.EXEC:swp 0 # number of swp insts executed
+system.cpu.iew.WB:consumers 90073384 # num instructions consuming a value
+system.cpu.iew.WB:count 96607772 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.596776 # average fanout of values written-back
+system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.WB:producers 53753594 # num instructions producing a value
+system.cpu.iew.WB:rate 0.861728 # insts written-back per cycle
+system.cpu.iew.WB:sent 96877677 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 2055865 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 89156 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 24681131 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 553822 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 1090188 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 5533285 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 103041048 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 23642288 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 2271319 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 97368620 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 1607 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 2697133 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 23177 # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked 17440 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 113868 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 30334 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.memOrderViolation 1330 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 2095638 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 788441 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 1330 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 76117 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 1979748 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 0.813516 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.813516 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntAlu 70327801 70.58% 70.58% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntMult 10479 0.01% 70.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 70.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 70.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 70.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 70.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 70.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 70.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 70.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 70.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 70.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 70.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 70.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 70.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 70.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 70.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 70.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 70.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 70.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 70.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 70.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 70.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 2 0.00% 70.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 11 0.00% 70.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 70.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 27 0.00% 70.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 70.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 3 0.00% 70.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 70.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemRead 24261779 24.35% 94.94% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemWrite 5039837 5.06% 100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::total 99639939 # Type of FU issued
+system.cpu.iq.ISSUE:fu_busy_cnt 491330 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.004931 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntAlu 430175 87.55% 87.55% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntMult 27 0.01% 87.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 87.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 87.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 87.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 87.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 87.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 87.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 87.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 87.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 87.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 87.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 87.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 87.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 87.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 87.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 87.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 87.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 87.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 87.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 87.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 87.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 87.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 87.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 87.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 87.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 87.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 87.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 87.56% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemRead 26408 5.37% 92.93% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemWrite 34720 7.07% 100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:issued_per_cycle::samples 112077802 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::mean 0.889025 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.090069 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0 47848976 42.69% 42.69% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1 42741533 38.14% 80.83% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2 14042267 12.53% 93.36% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3 4560980 4.07% 97.43% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4 789415 0.70% 98.13% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5 737896 0.66% 98.79% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6 1220893 1.09% 99.88% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7 128302 0.11% 99.99% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::8 7540 0.01% 100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::total 112077802 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate 0.888775 # Inst issue rate
+system.cpu.iq.iqInstsAdded 102487226 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 99639939 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 553822 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 9797863 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 388 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 9100 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 13596507 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.inst_hits 0 # ITB inst hits
+system.cpu.itb.inst_misses 0 # ITB inst misses
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.l2cache.ReadExReq_accesses 46574 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34284.629133 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31026.465938 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_hits 32027 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency 498738500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 0.312342 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 14547 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 451342000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.312342 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 14547 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 904214 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34294.794795 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31103.850051 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 903215 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 34260500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.001105 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 999 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_hits 12 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_miss_latency 30699500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001092 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 987 # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 943195 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 943195 # number of Writeback hits
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 103.008184 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 950788 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34285.282388 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31031.382773 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 935242 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 532999000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.016351 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 15546 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 12 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 482041500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.016338 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 15534 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0 0.012324 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.246682 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 403.843593 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 8083.268341 # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses 950788 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34285.282388 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31031.382773 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 935242 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 532999000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.016351 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 15546 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 12 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 482041500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.016338 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 15534 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.replacements 709 # number of replacements
+system.cpu.l2cache.sampled_refs 15518 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 8487.111934 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 1598481 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 32 # number of writebacks
+system.cpu.memDep0.conflictingLoads 436025 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 249497 # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads 24681131 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 5533285 # Number of stores inserted to the mem dependence unit.
+system.cpu.numCycles 112109302 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 294826 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps 72061910 # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents 4906 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 29931124 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 31548 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:RenameLookups 277459118 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 106593773 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 83924761 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 72730212 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 2697133 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 723330 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 11862848 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 5701177 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 592742 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 1065555 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 576556 # count of temporary serializing insts renamed
+system.cpu.timesIdled 1292 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.workload.PROG:num_syscalls 442 # Number of system calls
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=DerivO3CPU
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+issueToExecuteDelay=1
+issueWidth=8
+itb=system.cpu.itb
+localCtrBits=2
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+localHistoryTableSize=2048
+localPredictorSize=2048
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+max_loads_any_thread=0
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+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
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+phase=0
+predType=tournament
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
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+smtROBThreshold=100
+squashWidth=8
+system=system
+tracer=system.cpu.tracer
+trapLatency=13
+wbDepth=1
+wbWidth=8
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
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+forward_snoops=true
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+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
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+size=262144
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=ArmTLB
+size=64
+
+[system.cpu.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+children=opList
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+opList=system.cpu.fuPool.FUList0.opList
+
+[system.cpu.fuPool.FUList0.opList]
+type=OpDesc
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+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
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+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
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+
+[system.cpu.fuPool.FUList1.opList1]
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+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
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+
+[system.cpu.fuPool.FUList2.opList1]
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+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
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+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
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+opClass=FloatMult
+opLat=4
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
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+opClass=FloatDiv
+opLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList4.opList
+
+[system.cpu.fuPool.FUList4.opList]
+type=OpDesc
+issueLat=1
+opClass=MemRead
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+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
+count=4
+opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+
+[system.cpu.fuPool.FUList5.opList00]
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+
+[system.cpu.fuPool.FUList5.opList01]
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+
+[system.cpu.fuPool.FUList5.opList03]
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+[system.cpu.fuPool.FUList5.opList04]
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+
+[system.cpu.fuPool.FUList5.opList06]
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+
+[system.cpu.fuPool.FUList5.opList07]
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+
+[system.cpu.fuPool.FUList5.opList08]
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+
+[system.cpu.fuPool.FUList5.opList09]
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+[system.cpu.fuPool.FUList5.opList10]
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+[system.cpu.fuPool.FUList5.opList11]
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+
+[system.cpu.fuPool.FUList5.opList12]
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+
+[system.cpu.fuPool.FUList5.opList13]
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+
+[system.cpu.fuPool.FUList5.opList14]
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+
+[system.cpu.fuPool.FUList5.opList15]
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+
+[system.cpu.fuPool.FUList5.opList16]
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+
+[system.cpu.fuPool.FUList5.opList17]
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+
+[system.cpu.fuPool.FUList5.opList18]
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+
+[system.cpu.fuPool.FUList5.opList19]
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+
+[system.cpu.fuPool.FUList6]
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+
+[system.cpu.fuPool.FUList6.opList]
+type=OpDesc
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+[system.cpu.fuPool.FUList7]
+type=FUDesc
+children=opList0 opList1
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+opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+
+[system.cpu.fuPool.FUList7.opList0]
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+
+[system.cpu.fuPool.FUList7.opList1]
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+
+[system.cpu.fuPool.FUList8]
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+
+[system.cpu.fuPool.FUList8.opList]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
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+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=ArmTLB
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=parser 2.1.dict -batch
+cwd=build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/parser
+gid=100
+input=/chips/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=114600000000
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[0]
+
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
+warn: Bad interworking branch address 0xbeffffee.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0xbeffffee.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x2.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x2.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0xbeffffee.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0xbeffffee.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0xbeffffee.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0xbeffffee.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0xbeffffee.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0xbeffffee.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0xbeffffee.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0xbeffffee.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0xbeffffee.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0xbeffffee.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0xbeffffee.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0xbeffffee.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0xbeffffee.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0xbeffffee.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0xbeffffee.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0xbeffffee.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0xbeffffee.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0xbeffffee.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0xbeffffee.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0xbeffffee.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0xbeffffee.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0xbeffffee.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0xbeffffee.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x402807b6.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x6.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x6.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x6.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x6.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0xbeffffee.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0xbeffffee.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0xbeffffee.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0xbeffffee.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0xbeffffee.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0xbeffffee.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x403387de.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0xa.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0xa.
+For more information see: http://www.m5sim.org/warn/55f199fd
+hack: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jan 11 2011 18:16:01
+M5 revision b39a8457b332 7816 default ext/o3_regressions.patch qtip tip
+M5 started Jan 12 2011 03:20:30
+M5 executing on u200439-lin.austin.arm.com
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+
+ Reading the dictionary files: *************************************************
+
+
+Welcome to the Link Parser -- Version 2.1
+
+ Copyright (C) 1991-1995 Daniel Sleator and Davy Temperley
+
+Processing sentences in batch mode
+
+info: Increasing stack size by one page.
+Echoing of input sentence turned on.
+* as had expected the party to be a success , it was a success
+* do you know where John 's
+* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor
+info: Increasing stack size by one page.
+* how fast the program is it
+* I am wondering whether to invite to the party
+* I gave him for his birthday it
+* I thought terrible after our discussion
+* I wonder how much money have you earned
+* Janet who is an expert on dogs helped me choose one
+* she interviewed more programmers than was hired
+* such flowers are found chiefly particularly in Europe
+* the dogs some of which were very large ran after the man
+* the man whom I play tennis is here
+* there is going to be an important meeting January
+* to pretend that our program is usable in its current form would be happy
+* we're thinking about going to a movie this theater
+* which dog you said you chased
+- also invited to the meeting were several prominent scientists
+- he ran home so quickly that his mother could hardly believe he had called from school
+- so many people attended that they spilled over into several neighboring fields
+- voting in favor of the bill were 36 Republicans and 4 moderate Democrats
+: Grace may not be possible to fix the problem
+ any program as good as ours should be useful
+ biochemically , I think the experiment has a lot of problems
+ Fred has had five years of experience as a programmer
+ he is looking for another job
+ how did John do it
+ how many more people do you think will come
+ how much more spilled
+ I have more money than John has time
+ I made it clear that I was angry
+ I wonder how John did it
+ I wonder how much more quickly he ran
+ invite John and whoever else you want to invite
+ it is easier to ignore the problem than it is to solve it
+ many who initially supported Thomas later changed their minds
+ neither Mary nor Louise are coming to the party
+ she interviewed more programmers than were hired
+ telling Joe that Sue was coming to the party would create a real problem
+ the man with whom I play tennis is here
+ there is a dog in the park
+ this is not the man we know and love
+ we like to eat at restaurants , usually on weekends
+ what did John say he thought you should do
+ about 2 million people attended
+ the five best costumes got prizes
+No errors!
+Exiting @ tick 365535797000 because target called exit()
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 95936 # Simulator instruction rate (inst/s)
+host_mem_usage 255716 # Number of bytes of host memory used
+host_seconds 5851.87 # Real time elapsed on the host
+host_tick_rate 62464794 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 561403855 # Number of instructions simulated
+sim_seconds 0.365536 # Number of seconds simulated
+sim_ticks 365535797000 # Number of ticks simulated
+system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.BTBHits 140412857 # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 174405829 # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect 15516134 # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted 191856696 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 191856696 # Number of BP lookups
+system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
+system.cpu.commit.COM:branches 110089780 # Number of branches committed
+system.cpu.commit.COM:bw_lim_events 3543910 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
+system.cpu.commit.COM:committed_per_cycle::samples 660408748 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean 0.850085 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev 1.259950 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0 341979114 51.78% 51.78% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1 195474584 29.60% 81.38% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2 65236254 9.88% 91.26% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3 25100650 3.80% 95.06% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4 18282819 2.77% 97.83% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5 7231568 1.10% 98.92% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6 2404526 0.36% 99.29% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7 1155323 0.17% 99.46% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8 3543910 0.54% 100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total 660408748 # Number of insts commited each cycle
+system.cpu.commit.COM:count 561403855 # Number of instructions committed
+system.cpu.commit.COM:loads 128127024 # Number of loads committed
+system.cpu.commit.COM:membars 0 # Number of memory barriers committed
+system.cpu.commit.COM:refs 184987501 # Number of memory references committed
+system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
+system.cpu.commit.branchMispredicts 27361456 # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 561403855 # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls 157189 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts 399600068 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 561403855 # Number of Instructions Simulated
+system.cpu.committedInsts_total 561403855 # Number of Instructions Simulated
+system.cpu.cpi 1.302220 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.302220 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 149781892 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 10115.689557 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6757.918127 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 148783591 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 10098503000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.006665 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 998301 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 174053 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 5570200500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.005503 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 824248 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 55727847 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 14769.740800 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13602.051977 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 54444667 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 18952236000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.023026 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 1283180 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 935759 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 4725638500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.006234 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 347421 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 173.452238 # Average number of references to valid blocks.
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 205509739 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 12733.281145 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 8787.327308 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 203228258 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 29050739000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.011102 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 2281481 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 1109812 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 10295839000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.005701 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 1171669 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0 0.992538 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 4065.435193 # Average occupied blocks per context
+system.cpu.dcache.overall_accesses 205509739 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 12733.281145 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 8787.327308 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 203228258 # number of overall hits
+system.cpu.dcache.overall_miss_latency 29050739000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.011102 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 2281481 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 1109812 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 10295839000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.005701 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 1171669 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.replacements 1167571 # number of replacements
+system.cpu.dcache.sampled_refs 1171667 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 4065.435193 # Cycle average of tags in use
+system.cpu.dcache.total_refs 203228263 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 6053773000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 1048319 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 23914899 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:DecodedInsts 1082691365 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 293791436 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 339619753 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 66259738 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:UnblockCycles 3082660 # Number of cycles decode is unblocking
+system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.inst_hits 0 # ITB inst hits
+system.cpu.dtb.inst_misses 0 # ITB inst misses
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.read_hits 0 # DTB read hits
+system.cpu.dtb.read_misses 0 # DTB read misses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.write_hits 0 # DTB write hits
+system.cpu.dtb.write_misses 0 # DTB write misses
+system.cpu.fetch.Branches 191856696 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 122785155 # Number of cache lines fetched
+system.cpu.fetch.Cycles 351913139 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 3732953 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 938955668 # Number of instructions fetch has processed
+system.cpu.fetch.MiscStallCycles 5443516 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.SquashCycles 27647770 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.262432 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 122785155 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 140412857 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 1.284355 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples 726668486 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.538402 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.455586 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 375480392 51.67% 51.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 167711007 23.08% 74.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 28511073 3.92% 78.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 34539499 4.75% 83.43% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 26732700 3.68% 87.11% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 10963415 1.51% 88.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 11441350 1.57% 90.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 11151746 1.53% 91.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 60137304 8.28% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 726668486 # Number of instructions fetched each cycle (Total)
+system.cpu.icache.ReadReq_accesses 122785155 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 13335.070892 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 9658.160050 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 122768369 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 223842500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000137 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 16786 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 916 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 153275000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000129 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 15870 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 7736.852092 # Average number of references to valid blocks.
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 122785155 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 13335.070892 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 9658.160050 # average overall mshr miss latency
+system.cpu.icache.demand_hits 122768369 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 223842500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000137 # miss rate for demand accesses
+system.cpu.icache.demand_misses 16786 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 916 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 153275000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000129 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 15870 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0 0.542928 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 1111.916228 # Average occupied blocks per context
+system.cpu.icache.overall_accesses 122785155 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 13335.070892 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 9658.160050 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 122768369 # number of overall hits
+system.cpu.icache.overall_miss_latency 223842500 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000137 # miss rate for overall accesses
+system.cpu.icache.overall_misses 16786 # number of overall misses
+system.cpu.icache.overall_mshr_hits 916 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 153275000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000129 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 15870 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.replacements 14020 # number of replacements
+system.cpu.icache.sampled_refs 15868 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 1111.916228 # Cycle average of tags in use
+system.cpu.icache.total_refs 122768369 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idleCycles 4403109 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 125406817 # Number of branches executed
+system.cpu.iew.EXEC:nop 0 # number of nop insts executed
+system.cpu.iew.EXEC:rate 0.996154 # Inst execution rate
+system.cpu.iew.EXEC:refs 229537979 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 71989836 # Number of stores executed
+system.cpu.iew.EXEC:swp 0 # number of swp insts executed
+system.cpu.iew.WB:consumers 715317405 # num instructions consuming a value
+system.cpu.iew.WB:count 674936623 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.509545 # average fanout of values written-back
+system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.WB:producers 364486134 # num instructions producing a value
+system.cpu.iew.WB:rate 0.923215 # insts written-back per cycle
+system.cpu.iew.WB:sent 715720315 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 30103584 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 2644883 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 200154824 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 162257 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 12097440 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 140083731 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 960991852 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 157548143 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 31983856 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 728259959 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 123835 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu.iew.iewLSQFullEvents 3633 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 66259738 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 187555 # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 4454393 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 9891 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.memOrderViolation 352056 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 12768 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 72027799 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 83223254 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 352056 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 15636111 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 14467473 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 0.767919 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.767919 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntAlu 514982916 67.74% 67.74% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntMult 348808 0.05% 67.79% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 67.79% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatAdd 120 0.00% 67.79% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 67.79% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.79% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.79% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.79% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.79% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 67.79% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 67.79% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 67.79% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 67.79% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 67.79% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 67.79% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 67.79% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 67.79% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 67.79% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 67.79% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 67.79% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 67.79% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 67.79% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 67.79% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 67.79% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 67.79% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 3 0.00% 67.79% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 67.79% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 67.79% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 67.79% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemRead 162349838 21.35% 89.14% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemWrite 82562130 10.86% 100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::total 760243815 # Type of FU issued
+system.cpu.iq.ISSUE:fu_busy_cnt 11461228 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.015076 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntAlu 133776 1.17% 1.17% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 1.17% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 1.17% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 1.17% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 1.17% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 1.17% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 1.17% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 1.17% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 1.17% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 1.17% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 1.17% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 1.17% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 1.17% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 1.17% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 1.17% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 1.17% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 1.17% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 1.17% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 1.17% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 1.17% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 1.17% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 1.17% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 1.17% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 1.17% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 1.17% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 1.17% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 1.17% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 1.17% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 1.17% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemRead 5928179 51.72% 52.89% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemWrite 5399273 47.11% 100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:issued_per_cycle::samples 726668486 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::mean 1.046204 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.384447 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0 339626130 46.74% 46.74% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1 195069580 26.84% 73.58% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2 101922937 14.03% 87.61% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3 40650184 5.59% 93.20% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4 24674774 3.40% 96.60% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5 15399691 2.12% 98.72% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6 3388059 0.47% 99.18% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7 4145144 0.57% 99.75% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::8 1791987 0.25% 100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::total 726668486 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate 1.039903 # Inst issue rate
+system.cpu.iq.iqInstsAdded 960829595 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 760243815 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 162257 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 389023744 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 7997557 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 5068 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 710003502 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.inst_hits 0 # ITB inst hits
+system.cpu.itb.inst_misses 0 # ITB inst misses
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.l2cache.ReadExReq_accesses 347847 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34254.310886 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31004.170745 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_hits 228324 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency 4094178000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 0.343608 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 119523 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 3705711500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.343608 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 119523 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 839688 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34183.859863 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.526653 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 724943 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 3922427000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.136652 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 114745 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_hits 30 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_miss_latency 3558405000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.136616 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 114715 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 2 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_hits 2 # number of UpgradeReq hits
+system.cpu.l2cache.Writeback_accesses 1048319 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 1048319 # number of Writeback hits
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 6.336020 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 1187535 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34219.803814 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31011.691101 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 953267 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 8016605000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.197273 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 234268 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 30 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 7264116500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.197247 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 234238 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0 0.185686 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.450094 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 6084.559967 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 14748.682079 # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses 1187535 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34219.803814 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31011.691101 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 953267 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 8016605000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.197273 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 234268 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 30 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 7264116500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.197247 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 234238 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.replacements 215168 # number of replacements
+system.cpu.l2cache.sampled_refs 235364 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 20833.242046 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 1491271 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 262458362000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 171581 # number of writebacks
+system.cpu.memDep0.conflictingLoads 60170710 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 74734099 # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads 200154824 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 140083731 # Number of stores inserted to the mem dependence unit.
+system.cpu.numCycles 731071595 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 7125233 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps 435368498 # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents 5221350 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 309286671 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 9288405 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents 16 # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups 2644676144 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 1043986494 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 713690265 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 326862324 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 66259738 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 15428382 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 278321764 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 1706138 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 233255 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 48704887 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 185624 # count of temporary serializing insts renamed
+system.cpu.timesIdled 93433 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.workload.PROG:num_syscalls 548 # Number of system calls
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=DerivO3CPU
+children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+cachePorts=200
+checker=Null
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+cpu_id=0
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+defer_registration=false
+dispatchWidth=8
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+issueToExecuteDelay=1
+issueWidth=8
+itb=system.cpu.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+phase=0
+predType=tournament
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+squashWidth=8
+system=system
+tracer=system.cpu.tracer
+trapLatency=13
+wbDepth=1
+wbWidth=8
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=ArmTLB
+size=64
+
+[system.cpu.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+children=opList
+count=6
+opList=system.cpu.fuPool.FUList0.opList
+
+[system.cpu.fuPool.FUList0.opList]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntMult
+opLat=3
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+issueLat=19
+opClass=IntDiv
+opLat=20
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList4.opList
+
+[system.cpu.fuPool.FUList4.opList]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
+count=4
+opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+
+[system.cpu.fuPool.FUList5.opList00]
+type=OpDesc
+issueLat=1
+opClass=SimdAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList01]
+type=OpDesc
+issueLat=1
+opClass=SimdAddAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList02]
+type=OpDesc
+issueLat=1
+opClass=SimdAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList03]
+type=OpDesc
+issueLat=1
+opClass=SimdCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList04]
+type=OpDesc
+issueLat=1
+opClass=SimdCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList05]
+type=OpDesc
+issueLat=1
+opClass=SimdMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList06]
+type=OpDesc
+issueLat=1
+opClass=SimdMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList07]
+type=OpDesc
+issueLat=1
+opClass=SimdMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList08]
+type=OpDesc
+issueLat=1
+opClass=SimdShift
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList09]
+type=OpDesc
+issueLat=1
+opClass=SimdShiftAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList10]
+type=OpDesc
+issueLat=1
+opClass=SimdSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList11]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList12]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList13]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList14]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList15]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatDiv
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList16]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList17]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList18]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList19]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList6.opList
+
+[system.cpu.fuPool.FUList6.opList]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList7.opList1]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList8]
+type=FUDesc
+children=opList
+count=1
+opList=system.cpu.fuPool.FUList8.opList
+
+[system.cpu.fuPool.FUList8.opList]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=ArmTLB
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
+cwd=build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/eon
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[0]
+
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+getting pixel output filename pixels_out.cook
+opening control file chair.control.cook
+opening camera file chair.camera
+opening surfaces file chair.surfaces
+reading data
+processing 8parts
+Grid measure is 6 by 3.0001 by 6
+cell dimension is 0.863065
+Creating grid for list of length 21
+Grid size = 7 by 4 by 7
+Total occupancy = 236
+reading control stream
+reading camera stream
+Writing to chair.cook.ppm
+calculating 15 by 15 image with 196 samples
+col 0. . .
+col 1. . .
+col 2. . .
+col 3. . .
+col 4. . .
+col 5. . .
+col 6. . .
+col 7. . .
+col 8. . .
+col 9. . .
+col 10. . .
+col 11. . .
+col 12. . .
+col 13. . .
+col 14. . .
+Writing to chair.cook.ppm
+0 8 14
+1 8 14
+2 8 14
+3 8 14
+4 8 14
+5 8 14
+6 8 14
+7 8 14
+8 8 14
+9 8 14
+10 8 14
+11 8 14
+12 8 14
+13 8 14
+14 8 14
+warn: Bad interworking branch address 0x7ceeeeee.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7dfefefe.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7cb6b6b6.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7e929292.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7e9a9a9a.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7e9a9a9a.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7ea2a2a2.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7e868686.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7da6a6a6.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7eaeaeae.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7deaeaea.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7dc2c2c2.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7d828282.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7ea6a6a6.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7e9e9e9e.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7de2e2e2.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7cfefefe.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7d9e9e9e.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7dfefefe.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7e9a9a9a.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7e9a9a9a.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7ddadada.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7e828282.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7e8a8a8a.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7ea2a2a2.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7eb6b6b6.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7edadada.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7ebababa.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7ef6f6f6.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x80868686.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7faeaeae.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7faaaaaa.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7f8e8e8e.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7ee2e2e2.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7f868686.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7fa6a6a6.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7f969696.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7fd2d2d2.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7fcecece.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7ff6f6f6.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7feaeaea.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7fdadada.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7fe6e6e6.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7f8a8a8a.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7feaeaea.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7fdedede.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7feeeeee.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7ff2f2f2.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7ff2f2f2.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7feeeeee.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7fd6d6d6.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7fd2d2d2.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0x7faeaeae.
+For more information see: http://www.m5sim.org/warn/55f199fd
+hack: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jan 11 2011 18:16:01
+M5 revision b39a8457b332 7816 default ext/o3_regressions.patch qtip tip
+M5 started Jan 12 2011 03:29:33
+M5 executing on u200439-lin.austin.arm.com
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+Eon, Version 1.1
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+OO-style eon Time= 0.210000
+Exiting @ tick 215422929500 because target called exit()
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 100561 # Simulator instruction rate (inst/s)
+host_mem_usage 266348 # Number of bytes of host memory used
+host_seconds 3428.53 # Real time elapsed on the host
+host_tick_rate 62832373 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 344777955 # Number of instructions simulated
+sim_seconds 0.215423 # Number of seconds simulated
+sim_ticks 215422929500 # Number of ticks simulated
+system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.BTBHits 29670463 # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 36719834 # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect 7622670 # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted 36869176 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 36869176 # Number of BP lookups
+system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
+system.cpu.commit.COM:branches 28188953 # Number of branches committed
+system.cpu.commit.COM:bw_lim_events 5177395 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
+system.cpu.commit.COM:committed_per_cycle::samples 417225954 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean 0.826358 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev 1.412065 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0 233100827 55.87% 55.87% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1 116424181 27.90% 83.77% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2 32132758 7.70% 91.48% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3 14133629 3.39% 94.86% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4 7357054 1.76% 96.63% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5 4244458 1.02% 97.64% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6 2971859 0.71% 98.36% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7 1683793 0.40% 98.76% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8 5177395 1.24% 100.00% # Number of insts commited each cycle
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+system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total 417225954 # Number of insts commited each cycle
+system.cpu.commit.COM:count 344777955 # Number of instructions committed
+system.cpu.commit.COM:loads 94652977 # Number of loads committed
+system.cpu.commit.COM:membars 0 # Number of memory barriers committed
+system.cpu.commit.COM:refs 177028572 # Number of memory references committed
+system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
+system.cpu.commit.branchMispredicts 9986423 # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 344777955 # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls 3533298 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts 48561535 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 344777955 # Number of Instructions Simulated
+system.cpu.committedInsts_total 344777955 # Number of Instructions Simulated
+system.cpu.cpi 1.249633 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.249633 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 98212602 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 32812.217924 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 30418.895349 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 98209500 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 101783500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.000032 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 3102 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 1382 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 52320500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.000018 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 1720 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 82063572 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 29748.238774 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35491.403509 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 82044977 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 553168500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.000227 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 18595 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 15745 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 101150500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.000035 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 2850 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 11781.250000 # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 39442.992779 # Average number of references to valid blocks.
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 16 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 188500 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 180276174 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 30186.293036 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 33582.275711 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 180254477 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 654952000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.000120 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 21697 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 17127 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 153471000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 4570 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0 0.755653 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 3095.155920 # Average occupied blocks per context
+system.cpu.dcache.overall_accesses 180276174 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 30186.293036 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 33582.275711 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 180254477 # number of overall hits
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+system.cpu.dcache.overall_miss_rate 0.000120 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 21697 # number of overall misses
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+system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 4570 # number of overall MSHR misses
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+system.cpu.dcache.replacements 1402 # number of replacements
+system.cpu.dcache.sampled_refs 4570 # Sample count of references to valid blocks.
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+system.cpu.dcache.tagsinuse 3095.155920 # Cycle average of tags in use
+system.cpu.dcache.total_refs 180254477 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 1028 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 135683877 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:DecodedInsts 445047974 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 110691347 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 165193341 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 13510660 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:UnblockCycles 5657389 # Number of cycles decode is unblocking
+system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.inst_hits 0 # ITB inst hits
+system.cpu.dtb.inst_misses 0 # ITB inst misses
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.read_hits 0 # DTB read hits
+system.cpu.dtb.read_misses 0 # DTB read misses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.write_hits 0 # DTB write hits
+system.cpu.dtb.write_misses 0 # DTB write misses
+system.cpu.fetch.Branches 36869176 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 45676058 # Number of cache lines fetched
+system.cpu.fetch.Cycles 181360432 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 631539 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 363476722 # Number of instructions fetch has processed
+system.cpu.fetch.MiscStallCycles 18599 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.SquashCycles 9990891 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.085574 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 45676058 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 29670463 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 0.843635 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples 430736614 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.090672 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 1.994313 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 252892328 58.71% 58.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 95422194 22.15% 80.86% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 21830959 5.07% 85.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 14061343 3.26% 89.20% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 11029779 2.56% 91.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 8719423 2.02% 93.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 4691834 1.09% 94.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 4052981 0.94% 95.81% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 18035773 4.19% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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+system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 430736614 # Number of instructions fetched each cycle (Total)
+system.cpu.icache.ReadReq_accesses 45676058 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 11498.094859 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 7998.634691 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 45658474 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 202182500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000385 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 17584 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 738 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 134745000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000369 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 16846 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 2710.666944 # Average number of references to valid blocks.
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 45676058 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 11498.094859 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 7998.634691 # average overall mshr miss latency
+system.cpu.icache.demand_hits 45658474 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 202182500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000385 # miss rate for demand accesses
+system.cpu.icache.demand_misses 17584 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 738 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 134745000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000369 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 16846 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0 0.897245 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 1837.557212 # Average occupied blocks per context
+system.cpu.icache.overall_accesses 45676058 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 11498.094859 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 7998.634691 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 45658474 # number of overall hits
+system.cpu.icache.overall_miss_latency 202182500 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000385 # miss rate for overall accesses
+system.cpu.icache.overall_misses 17584 # number of overall misses
+system.cpu.icache.overall_mshr_hits 738 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 134745000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000369 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 16846 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.replacements 14975 # number of replacements
+system.cpu.icache.sampled_refs 16844 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 1837.557212 # Cycle average of tags in use
+system.cpu.icache.total_refs 45658474 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idleCycles 109246 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 29572211 # Number of branches executed
+system.cpu.iew.EXEC:nop 0 # number of nop insts executed
+system.cpu.iew.EXEC:rate 0.858504 # Inst execution rate
+system.cpu.iew.EXEC:refs 185717004 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 85614435 # Number of stores executed
+system.cpu.iew.EXEC:swp 0 # number of swp insts executed
+system.cpu.iew.WB:consumers 264958674 # num instructions consuming a value
+system.cpu.iew.WB:count 365790604 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.549025 # average fanout of values written-back
+system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.WB:producers 145468948 # num instructions producing a value
+system.cpu.iew.WB:rate 0.849006 # insts written-back per cycle
+system.cpu.iew.WB:sent 367353689 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 10421858 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 4450 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 108215524 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 3540937 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 11257749 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 93620853 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 393342022 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 100102569 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 7571412 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 369883065 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 69 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu.iew.iewLSQFullEvents 9 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 13510660 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 176 # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked 37 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 651720 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 443 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.memOrderViolation 6487 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 33 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 13562546 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 11245258 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 6487 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 2859204 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 7562654 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 0.800235 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.800235 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntAlu 130407630 34.55% 34.55% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntMult 2146058 0.57% 35.12% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 35.12% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatAdd 3 0.00% 35.12% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 35.12% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 35.12% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 35.12% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 35.12% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 35.12% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 35.12% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 35.12% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 35.12% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdCmp 679 0.00% 35.12% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdCvt 2 0.00% 35.12% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 35.12% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 35.12% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 35.12% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 35.12% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 35.12% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 35.12% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 6735975 1.78% 36.90% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 36.90% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 8317099 2.20% 39.11% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 3313873 0.88% 39.98% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 1566398 0.41% 40.40% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 20555034 5.45% 45.84% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 7151488 1.89% 47.74% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 7075439 1.87% 49.61% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 175286 0.05% 49.66% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemRead 102612479 27.19% 76.85% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemWrite 87397034 23.15% 100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::total 377454477 # Type of FU issued
+system.cpu.iq.ISSUE:fu_busy_cnt 6999236 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.018543 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntAlu 204 0.00% 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntMult 5040 0.07% 0.07% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.07% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.07% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.07% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.07% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.07% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.07% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.07% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.07% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.07% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.07% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.07% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.07% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.07% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.07% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.07% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.07% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.07% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.07% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 70 0.00% 0.08% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.08% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.08% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 715 0.01% 0.09% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 3 0.00% 0.09% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 145523 2.08% 2.17% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMult 588 0.01% 2.17% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 183278 2.62% 4.79% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 4.79% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemRead 4924134 70.35% 75.14% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemWrite 1739681 24.86% 100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:issued_per_cycle::samples 430736614 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::mean 0.876300 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.213056 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0 218913895 50.82% 50.82% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1 123057011 28.57% 79.39% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2 46006225 10.68% 90.07% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3 20712551 4.81% 94.88% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4 13744591 3.19% 98.07% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5 5457639 1.27% 99.34% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6 2167994 0.50% 99.84% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7 440824 0.10% 99.95% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::8 235884 0.05% 100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::total 430736614 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate 0.876078 # Inst issue rate
+system.cpu.iq.iqInstsAdded 389801085 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 377454477 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 3540937 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 45444738 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 803126 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 7639 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 100178963 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.inst_hits 0 # ITB inst hits
+system.cpu.itb.inst_misses 0 # ITB inst misses
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.l2cache.ReadExReq_accesses 2850 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34410.695376 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31218.319802 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_hits 17 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency 97485500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 0.994035 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 2833 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 88441500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.994035 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 2833 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 18566 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34300.665596 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31144.036271 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 14209 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 149448000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.234676 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 4357 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_hits 56 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_miss_latency 133950500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.231660 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 4301 # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 1028 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 1028 # number of Writeback hits
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 2.731600 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 21416 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34344.019471 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31173.535184 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 14226 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 246933500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.335730 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 7190 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 56 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 222392000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.333115 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 7134 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0 0.104167 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.011647 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 3413.355602 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 381.656203 # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses 21416 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34344.019471 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31173.535184 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 14226 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 246933500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.335730 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 7190 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 56 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 222392000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.333115 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 7134 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.replacements 55 # number of replacements
+system.cpu.l2cache.sampled_refs 5231 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 3795.011805 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 14289 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 0 # number of writebacks
+system.cpu.memDep0.conflictingLoads 34606299 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 43565672 # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads 108215524 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 93620853 # Number of stores inserted to the mem dependence unit.
+system.cpu.numCycles 430845860 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 2009946 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps 340171955 # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents 2410 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 122720704 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 4353276 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:RenameLookups 1678823809 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 427512242 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 413848674 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 159405057 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 13510660 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 15892138 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 73676716 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 117198109 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 12788197 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 37692287 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 3543781 # count of temporary serializing insts renamed
+system.cpu.timesIdled 2211 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.workload.PROG:num_syscalls 191 # Number of system calls
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=DerivO3CPU
+children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+cachePorts=200
+checker=Null
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
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+decodeToRenameDelay=1
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+dispatchWidth=8
+do_checkpoint_insts=true
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+dtb=system.cpu.dtb
+fetchToDecodeDelay=1
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+forwardComSize=5
+fuPool=system.cpu.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
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+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+issueToExecuteDelay=1
+issueWidth=8
+itb=system.cpu.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+phase=0
+predType=tournament
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+squashWidth=8
+system=system
+tracer=system.cpu.tracer
+trapLatency=13
+wbDepth=1
+wbWidth=8
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=ArmTLB
+size=64
+
+[system.cpu.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+children=opList
+count=6
+opList=system.cpu.fuPool.FUList0.opList
+
+[system.cpu.fuPool.FUList0.opList]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntMult
+opLat=3
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+issueLat=19
+opClass=IntDiv
+opLat=20
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList4.opList
+
+[system.cpu.fuPool.FUList4.opList]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
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+
+[system.cpu.tracer]
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+
+[system.cpu.workload]
+type=LiveProcess
+cmd=perlbmk -I. -I lib lgred.makerand.pl
+cwd=build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/o3-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/perlbmk
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
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+
+[system.membus]
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+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[0]
+
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
+warn: fcntl64(3, 2) passed through to host
+For more information see: http://www.m5sim.org/warn/a55e2c46
+warn: Bad interworking branch address 0x66.
+For more information see: http://www.m5sim.org/warn/55f199fd
+hack: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jan 11 2011 18:16:01
+M5 revision b39a8457b332 7816 default ext/o3_regressions.patch qtip tip
+M5 started Jan 12 2011 03:34:31
+M5 executing on u200439-lin.austin.arm.com
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/o3-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
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+Exiting @ tick 1106986290500 because target called exit()
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 126560 # Simulator instruction rate (inst/s)
+host_mem_usage 258084 # Number of bytes of host memory used
+host_seconds 14568.38 # Real time elapsed on the host
+host_tick_rate 75985562 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 1843766922 # Number of instructions simulated
+sim_seconds 1.106986 # Number of seconds simulated
+sim_ticks 1106986290500 # Number of ticks simulated
+system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.BTBHits 334577288 # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 553224056 # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect 46883845 # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted 562377077 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 562377077 # Number of BP lookups
+system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
+system.cpu.commit.COM:branches 258172659 # Number of branches committed
+system.cpu.commit.COM:bw_lim_events 41405242 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
+system.cpu.commit.COM:committed_per_cycle::samples 2026425019 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean 0.909862 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev 1.566343 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0 1126460049 55.59% 55.59% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1 528416767 26.08% 81.66% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2 168171926 8.30% 89.96% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3 70727286 3.49% 93.45% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4 47338472 2.34% 95.79% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5 23657957 1.17% 96.96% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6 13792404 0.68% 97.64% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7 6454916 0.32% 97.96% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8 41405242 2.04% 100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total 2026425019 # Number of insts commited each cycle
+system.cpu.commit.COM:count 1843766922 # Number of instructions committed
+system.cpu.commit.COM:loads 631405848 # Number of loads committed
+system.cpu.commit.COM:membars 0 # Number of memory barriers committed
+system.cpu.commit.COM:refs 908401145 # Number of memory references committed
+system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
+system.cpu.commit.branchMispredicts 84212939 # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 1843766922 # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls 188261 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts 1168824216 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 1843766922 # Number of Instructions Simulated
+system.cpu.committedInsts_total 1843766922 # Number of Instructions Simulated
+system.cpu.cpi 1.200788 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.200788 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 714254562 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 34305.778645 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34068.836125 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 712322725 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 66273172500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.002705 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 1931837 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 467831 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 49876980500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.002050 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 1464006 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 276945664 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 35173.008313 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32580.155094 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 276142350 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 28254970000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.002901 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 803314 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 730842 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 2361149000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.000262 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 72472 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 10666.666667 # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 643.332594 # Average number of references to valid blocks.
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 3 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 32000 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 991200226 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 34560.484046 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 33998.618594 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 988465075 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 94528142500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.002759 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 2735151 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 1198673 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 52238129500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.001550 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 1536478 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0 0.999786 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 4095.125013 # Average occupied blocks per context
+system.cpu.dcache.overall_accesses 991200226 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 34560.484046 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 33998.618594 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 988465075 # number of overall hits
+system.cpu.dcache.overall_miss_latency 94528142500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.002759 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 2735151 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 1198673 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 52238129500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.001550 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 1536478 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.replacements 1532380 # number of replacements
+system.cpu.dcache.sampled_refs 1536476 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 4095.125013 # Cycle average of tags in use
+system.cpu.dcache.total_refs 988465091 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 341946000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 106863 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 223702821 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:DecodedInsts 3748475932 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 853302528 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 949015552 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 187283417 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:UnblockCycles 404118 # Number of cycles decode is unblocking
+system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.inst_hits 0 # ITB inst hits
+system.cpu.dtb.inst_misses 0 # ITB inst misses
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.read_hits 0 # DTB read hits
+system.cpu.dtb.read_misses 0 # DTB read misses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.write_hits 0 # DTB write hits
+system.cpu.dtb.write_misses 0 # DTB write misses
+system.cpu.fetch.Branches 562377077 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 400588369 # Number of cache lines fetched
+system.cpu.fetch.Cycles 1002800662 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 11586078 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 2972268186 # Number of instructions fetch has processed
+system.cpu.fetch.MiscStallCycles 34327 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.SquashCycles 86966878 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.254013 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 400588369 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 334577288 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 1.342505 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples 2213708436 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.777306 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.798612 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 1213776786 54.83% 54.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 388415263 17.55% 72.38% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 93122307 4.21% 76.58% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 48895921 2.21% 78.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 60943546 2.75% 81.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 76981670 3.48% 85.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 16173404 0.73% 85.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 35829918 1.62% 87.37% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 279569621 12.63% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 2213708436 # Number of instructions fetched each cycle (Total)
+system.cpu.icache.ReadReq_accesses 400588369 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 8967.410787 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 5871.276669 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 400557684 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 275165000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000077 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 30685 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 1813 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 169515500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000072 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 28872 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 13875.010704 # Average number of references to valid blocks.
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 400588369 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 8967.410787 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 5871.276669 # average overall mshr miss latency
+system.cpu.icache.demand_hits 400557684 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 275165000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000077 # miss rate for demand accesses
+system.cpu.icache.demand_misses 30685 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 1813 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 169515500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000072 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 28872 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0 0.814790 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 1668.688983 # Average occupied blocks per context
+system.cpu.icache.overall_accesses 400588369 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 8967.410787 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 5871.276669 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 400557684 # number of overall hits
+system.cpu.icache.overall_miss_latency 275165000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000077 # miss rate for overall accesses
+system.cpu.icache.overall_misses 30685 # number of overall misses
+system.cpu.icache.overall_mshr_hits 1813 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 169515500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000072 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 28872 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.replacements 27162 # number of replacements
+system.cpu.icache.sampled_refs 28869 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 1668.688983 # Cycle average of tags in use
+system.cpu.icache.total_refs 400557684 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idleCycles 264146 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 328211890 # Number of branches executed
+system.cpu.iew.EXEC:nop 0 # number of nop insts executed
+system.cpu.iew.EXEC:rate 1.050140 # Inst execution rate
+system.cpu.iew.EXEC:refs 1122138305 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 367853547 # Number of stores executed
+system.cpu.iew.EXEC:swp 0 # number of swp insts executed
+system.cpu.iew.WB:consumers 2149738091 # num instructions consuming a value
+system.cpu.iew.WB:count 2244813187 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.548413 # average fanout of values written-back
+system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.WB:producers 1178945029 # num instructions producing a value
+system.cpu.iew.WB:rate 1.013930 # insts written-back per cycle
+system.cpu.iew.WB:sent 2267021093 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 93878046 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 4821399 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 976823890 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 9835077 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 65011205 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 487069954 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 3012606054 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 754284758 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 120224792 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 2324980968 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 971459 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu.iew.iewLSQFullEvents 242 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 187283417 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 1560904 # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked 14 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 12454380 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 4593 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.memOrderViolation 2755264 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 1382 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 345418041 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 210074657 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 2755264 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 45730558 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 48147488 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 0.832787 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.832787 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntAlu 1195936250 48.91% 48.91% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntMult 11168379 0.46% 49.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 49.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 49.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 49.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 49.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 49.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 49.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 49.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAdd 16846 0.00% 49.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 49.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 49.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 49.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 49.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 49.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 49.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 49.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 49.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 49.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 49.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 1375289 0.06% 49.42% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 49.42% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 6876473 0.28% 49.70% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 5501179 0.22% 49.93% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 49.93% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 23390230 0.96% 50.89% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 50.89% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 50.89% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 50.89% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemRead 793077281 32.43% 83.32% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemWrite 407863833 16.68% 100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::total 2445205760 # Type of FU issued
+system.cpu.iq.ISSUE:fu_busy_cnt 60724254 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.024834 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntAlu 337 0.00% 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntMult 24113 0.04% 0.04% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.04% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.04% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.04% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.04% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.04% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.04% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.04% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.04% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.04% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.04% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.04% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.04% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.04% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.04% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.04% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.04% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.04% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.04% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.04% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.04% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.04% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.04% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.04% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.04% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.04% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.04% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.04% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemRead 44167441 72.73% 72.77% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemWrite 16532363 27.23% 100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:issued_per_cycle::samples 2213708436 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::mean 1.104574 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.422277 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0 1044197875 47.17% 47.17% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1 536098097 24.22% 71.39% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2 282654634 12.77% 84.16% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3 162977150 7.36% 91.52% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4 122131975 5.52% 97.03% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5 40303840 1.82% 98.86% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6 15378768 0.69% 99.55% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7 7181539 0.32% 99.87% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::8 2784558 0.13% 100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::total 2213708436 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate 1.104443 # Inst issue rate
+system.cpu.iq.iqInstsAdded 3002770977 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 2445205760 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 9835077 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 1141885172 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 8344506 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 9646816 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 2082899377 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.inst_hits 0 # ITB inst hits
+system.cpu.itb.inst_misses 0 # ITB inst misses
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.l2cache.ReadExReq_accesses 72470 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34498.335527 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31001.225657 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_hits 6383 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency 2279891500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 0.911922 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 66087 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 2048778000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.911922 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 66087 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 1492876 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34237.383234 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.264277 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 77656 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 48453429500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.947982 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 1415220 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_hits 39 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_miss_latency 43870985000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.947956 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 1415181 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 2 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 2 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 62000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 2 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 106863 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 106863 # number of Writeback hits
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 0.056843 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 1565346 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34249.025354 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31000.307169 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 84039 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 50733321000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.946313 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 1481307 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 39 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 45919763000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.946288 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 1481268 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0 0.884785 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.091201 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 28992.645165 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 2988.461118 # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses 1565346 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34249.025354 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31000.307169 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 84039 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 50733321000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.946313 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 1481307 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 39 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 45919763000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.946288 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 1481268 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.replacements 1479999 # number of replacements
+system.cpu.l2cache.sampled_refs 1512721 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 31981.106283 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 85987 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 66099 # number of writebacks
+system.cpu.memDep0.conflictingLoads 48375882 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 167873780 # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads 976823890 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 487069954 # Number of stores inserted to the mem dependence unit.
+system.cpu.numCycles 2213972582 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 17658494 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps 1482327508 # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents 4825678 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 919120381 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 8406320 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents 1 # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups 9255875063 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 3353421712 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 2685986508 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 880460602 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 187283417 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 23975327 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 1203658997 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 185210215 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 19466962 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 226114375 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 13965391 # count of temporary serializing insts renamed
+system.cpu.timesIdled 87015 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.workload.PROG:num_syscalls 1411 # Number of system calls
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=DerivO3CPU
+children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+cachePorts=200
+checker=Null
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+cpu_id=0
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+defer_registration=false
+dispatchWidth=8
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+issueToExecuteDelay=1
+issueWidth=8
+itb=system.cpu.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+phase=0
+predType=tournament
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+squashWidth=8
+system=system
+tracer=system.cpu.tracer
+trapLatency=13
+wbDepth=1
+wbWidth=8
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=ArmTLB
+size=64
+
+[system.cpu.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+children=opList
+count=6
+opList=system.cpu.fuPool.FUList0.opList
+
+[system.cpu.fuPool.FUList0.opList]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntMult
+opLat=3
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+issueLat=19
+opClass=IntDiv
+opLat=20
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList4.opList
+
+[system.cpu.fuPool.FUList4.opList]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
+count=4
+opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+
+[system.cpu.fuPool.FUList5.opList00]
+type=OpDesc
+issueLat=1
+opClass=SimdAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList01]
+type=OpDesc
+issueLat=1
+opClass=SimdAddAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList02]
+type=OpDesc
+issueLat=1
+opClass=SimdAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList03]
+type=OpDesc
+issueLat=1
+opClass=SimdCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList04]
+type=OpDesc
+issueLat=1
+opClass=SimdCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList05]
+type=OpDesc
+issueLat=1
+opClass=SimdMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList06]
+type=OpDesc
+issueLat=1
+opClass=SimdMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList07]
+type=OpDesc
+issueLat=1
+opClass=SimdMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList08]
+type=OpDesc
+issueLat=1
+opClass=SimdShift
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList09]
+type=OpDesc
+issueLat=1
+opClass=SimdShiftAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList10]
+type=OpDesc
+issueLat=1
+opClass=SimdSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList11]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList12]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList13]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList14]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList15]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatDiv
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList16]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList17]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList18]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList19]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList6.opList
+
+[system.cpu.fuPool.FUList6.opList]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList7.opList1]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList8]
+type=FUDesc
+children=opList
+count=1
+opList=system.cpu.fuPool.FUList8.opList
+
+[system.cpu.fuPool.FUList8.opList]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=ArmTLB
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=vortex lendian.raw
+cwd=build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/vortex
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[0]
+
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
+warn: Bad interworking branch address 0x7002.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0xa.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0xa.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0xa.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0xa.
+For more information see: http://www.m5sim.org/warn/55f199fd
+warn: Bad interworking branch address 0xa.
+For more information see: http://www.m5sim.org/warn/55f199fd
+hack: be nice to actually delete the event here
--- /dev/null
+Redirecting stdout to build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing/simout
+Redirecting stderr to build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing/simerr
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jan 18 2011 03:54:36
+M5 revision 218f733923f8 7861 default qtip int/arm_gdb.patch tip
+M5 started Jan 18 2011 04:19:02
+M5 executing on aus-bc2-b9
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+Exiting @ tick 59259979500 because target called exit()
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 156565 # Simulator instruction rate (inst/s)
+host_mem_usage 260328 # Number of bytes of host memory used
+host_seconds 631.29 # Real time elapsed on the host
+host_tick_rate 93871242 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 98838077 # Number of instructions simulated
+sim_seconds 0.059260 # Number of seconds simulated
+sim_ticks 59259979500 # Number of ticks simulated
+system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.BTBHits 10631376 # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 17355232 # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect 914560 # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted 17451382 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 17451382 # Number of BP lookups
+system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
+system.cpu.commit.COM:branches 12133384 # Number of branches committed
+system.cpu.commit.COM:bw_lim_events 1268932 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
+system.cpu.commit.COM:committed_per_cycle::samples 114018884 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean 0.866857 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev 1.400756 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0 59418042 52.11% 52.11% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1 36575306 32.08% 84.19% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2 7815756 6.85% 91.05% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3 3335762 2.93% 93.97% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4 3218602 2.82% 96.79% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5 1142108 1.00% 97.80% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6 823063 0.72% 98.52% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7 421313 0.37% 98.89% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8 1268932 1.11% 100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total 114018884 # Number of insts commited each cycle
+system.cpu.commit.COM:count 98838077 # Number of instructions committed
+system.cpu.commit.COM:loads 27315295 # Number of loads committed
+system.cpu.commit.COM:membars 0 # Number of memory barriers committed
+system.cpu.commit.COM:refs 47871033 # Number of memory references committed
+system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
+system.cpu.commit.branchMispredicts 2496869 # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 98838077 # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls 667791 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts 18231626 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 98838077 # Number of Instructions Simulated
+system.cpu.committedInsts_total 98838077 # Number of Instructions Simulated
+system.cpu.cpi 1.199133 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.199133 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 28495397 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 22617.028157 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18828.183694 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 28388709 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 2412965500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.003744 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 106688 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 49985 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 1067614500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.001990 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 56703 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 19865820 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 32612.870291 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34110.136388 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 18320719 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 50390178500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.077777 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 1545101 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 1438347 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 3641393500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.005374 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 106754 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 21500 # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 285.786157 # Average number of references to valid blocks.
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 21500 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 48361217 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 31967.245211 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 28808.848810 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 46709428 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 52803144000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.034155 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 1651789 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 1488332 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 4709008000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.003380 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 163457 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0 0.995663 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 4078.236319 # Average occupied blocks per context
+system.cpu.dcache.overall_accesses 48361217 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 31967.245211 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 28808.848810 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 46709428 # number of overall hits
+system.cpu.dcache.overall_miss_latency 52803144000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.034155 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 1651789 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 1488332 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 4709008000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.003380 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 163457 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.replacements 159346 # number of replacements
+system.cpu.dcache.sampled_refs 163442 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 4078.236319 # Cycle average of tags in use
+system.cpu.dcache.total_refs 46709461 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 393981000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 124385 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 14942645 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:DecodedInsts 127014948 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 27511704 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 70998513 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 3514572 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:UnblockCycles 566022 # Number of cycles decode is unblocking
+system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.inst_hits 0 # ITB inst hits
+system.cpu.dtb.inst_misses 0 # ITB inst misses
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.read_hits 0 # DTB read hits
+system.cpu.dtb.read_misses 0 # DTB read misses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.write_hits 0 # DTB write hits
+system.cpu.dtb.write_misses 0 # DTB write misses
+system.cpu.fetch.Branches 17451382 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 12122688 # Number of cache lines fetched
+system.cpu.fetch.Cycles 73872074 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 96174 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 95885012 # Number of instructions fetch has processed
+system.cpu.fetch.MiscStallCycles 34128 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.SquashCycles 2507897 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.147244 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 12122688 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 10631376 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 0.809020 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples 117533456 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.108172 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 1.634523 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 43866274 37.32% 37.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 53998301 45.94% 83.27% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 9118937 7.76% 91.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 3358983 2.86% 93.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 1352835 1.15% 95.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 476061 0.41% 95.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 1116299 0.95% 96.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 521407 0.44% 96.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 3724359 3.17% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 117533456 # Number of instructions fetched each cycle (Total)
+system.cpu.icache.ReadReq_accesses 12122688 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 12759.423411 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 9476.994450 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 12098546 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 308038000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.001991 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 24142 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 539 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 223685500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.001947 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 23603 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 512.911056 # Average number of references to valid blocks.
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 12122688 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 12759.423411 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 9476.994450 # average overall mshr miss latency
+system.cpu.icache.demand_hits 12098546 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 308038000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.001991 # miss rate for demand accesses
+system.cpu.icache.demand_misses 24142 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 539 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 223685500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.001947 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 23603 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0 0.878284 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 1798.726213 # Average occupied blocks per context
+system.cpu.icache.overall_accesses 12122688 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 12759.423411 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 9476.994450 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 12098546 # number of overall hits
+system.cpu.icache.overall_miss_latency 308038000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.001991 # miss rate for overall accesses
+system.cpu.icache.overall_misses 24142 # number of overall misses
+system.cpu.icache.overall_mshr_hits 539 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 223685500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.001947 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 23603 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.replacements 21558 # number of replacements
+system.cpu.icache.sampled_refs 23588 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 1798.726213 # Cycle average of tags in use
+system.cpu.icache.total_refs 12098546 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idleCycles 986504 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 13347127 # Number of branches executed
+system.cpu.iew.EXEC:nop 0 # number of nop insts executed
+system.cpu.iew.EXEC:rate 0.903568 # Inst execution rate
+system.cpu.iew.EXEC:refs 50902903 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 21266898 # Number of stores executed
+system.cpu.iew.EXEC:swp 0 # number of swp insts executed
+system.cpu.iew.WB:consumers 83917531 # num instructions consuming a value
+system.cpu.iew.WB:count 104978436 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.516830 # average fanout of values written-back
+system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.WB:producers 43371139 # num instructions producing a value
+system.cpu.iew.WB:rate 0.885745 # insts written-back per cycle
+system.cpu.iew.WB:sent 106195350 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 2628455 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 987035 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 32508348 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 1016199 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 2305298 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 23389031 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 117101137 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 29636005 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 2065669 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 107090838 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 2107 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu.iew.iewLSQFullEvents 908 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 3514572 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 39558 # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 247077 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 2317 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.memOrderViolation 39532 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 7 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 5193052 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 2833293 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 39532 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 1768227 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 860228 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 0.833936 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.833936 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntAlu 57364104 52.55% 52.55% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntMult 80354 0.07% 52.63% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 52.63% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatAdd 124 0.00% 52.63% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 52.63% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 52.63% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 52.63% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 52.63% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 52.63% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAdd 1 0.00% 52.63% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 52.63% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 52.63% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 52.63% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 52.63% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 52.63% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 52.63% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 52.63% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 52.63% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 52.63% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 52.63% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 52.63% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 52.63% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 52.63% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 52.63% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 52.63% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 7 0.00% 52.63% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 52.63% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 52.63% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 52.63% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemRead 30140236 27.61% 80.24% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemWrite 21571681 19.76% 100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::total 109156507 # Type of FU issued
+system.cpu.iq.ISSUE:fu_busy_cnt 1323138 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.012121 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntAlu 1303 0.10% 0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemRead 1094336 82.71% 82.81% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemWrite 227499 17.19% 100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:issued_per_cycle::samples 117533456 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::mean 0.928727 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.126434 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0 53481972 45.50% 45.50% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1 35549975 30.25% 75.75% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2 18295748 15.57% 91.32% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3 5807729 4.94% 96.26% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4 2883694 2.45% 98.71% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5 1109227 0.94% 99.66% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6 329629 0.28% 99.94% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7 70692 0.06% 100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::8 4790 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::total 117533456 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate 0.920997 # Inst issue rate
+system.cpu.iq.iqInstsAdded 116084938 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 109156507 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 1016199 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 17094247 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 68325 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 348408 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 30276342 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.inst_hits 0 # ITB inst hits
+system.cpu.itb.inst_misses 0 # ITB inst misses
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.l2cache.ReadExReq_accesses 106739 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34385.177402 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31198.626723 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_hits 4429 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency 3517947500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 0.958506 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 102310 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 3191931500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.958506 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 102310 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 80290 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34268.509897 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31112.930905 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 46997 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 1140901500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.414659 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 33293 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_hits 78 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_miss_latency 1033416000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.413688 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 33215 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 15 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 3450 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31300 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_hits 5 # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_miss_latency 34500 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate 0.666667 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 10 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 313000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.666667 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 10 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 124385 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 124385 # number of Writeback hits
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 0.522459 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 187029 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34356.533410 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31177.624055 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 51426 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 4658849000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.725037 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 135603 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 78 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 4225347500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.724620 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 135525 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0 0.075665 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.490596 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 2479.385419 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 16075.863311 # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses 187029 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34356.533410 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31177.624055 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 51426 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 4658849000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.725037 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 135603 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 78 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 4225347500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.724620 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 135525 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.replacements 115260 # number of replacements
+system.cpu.l2cache.sampled_refs 134133 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 18555.248730 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 70079 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 88459 # number of writebacks
+system.cpu.memDep0.conflictingLoads 7990320 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 10924699 # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads 32508348 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 23389031 # Number of stores inserted to the mem dependence unit.
+system.cpu.numCycles 118519960 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 1866194 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps 74745628 # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents 1883 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 30389505 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 833530 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents 4 # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups 333412635 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 124050705 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 93358658 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 68672790 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 3514572 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 1591233 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 18613027 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 11499162 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 818368 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 3724500 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 819368 # count of temporary serializing insts renamed
+system.cpu.timesIdled 60726 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
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+
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+smtCommitPolicy=RoundRobin
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+squashWidth=8
+system=system
+tracer=system.cpu.tracer
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+wbDepth=1
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+workload=system.cpu.workload
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+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
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+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=ArmTLB
+size=64
+
+[system.cpu.fuPool]
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+
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+
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+count=4
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+opClass=IprAccess
+opLat=3
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=ArmTLB
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=bzip2 input.source 1
+cwd=build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/o3-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[0]
+
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
+hack: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jan 11 2011 18:16:01
+M5 revision b39a8457b332 7816 default ext/o3_regressions.patch qtip tip
+M5 started Jan 12 2011 03:57:47
+M5 executing on u200439-lin.austin.arm.com
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/o3-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+spec_init
+Loading Input Data
+Input data 1048576 bytes in length
+Compressing Input Data, level 7
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+Compressed data 198546 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Compressing Input Data, level 9
+Compressed data 198677 bytes in length
+Uncompressing Data
+Uncompressed data 1048576 bytes in length
+Uncompressed data compared correctly
+Tested 1MB buffer: OK!
+Exiting @ tick 736332221500 because target called exit()
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 165173 # Simulator instruction rate (inst/s)
+host_mem_usage 251872 # Number of bytes of host memory used
+host_seconds 10349.18 # Real time elapsed on the host
+host_tick_rate 71148819 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 1709408682 # Number of instructions simulated
+sim_seconds 0.736332 # Number of seconds simulated
+sim_ticks 736332221500 # Number of ticks simulated
+system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.BTBHits 251161589 # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 289953961 # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect 20139757 # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted 310539803 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 310539803 # Number of BP lookups
+system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
+system.cpu.commit.COM:branches 203576342 # Number of branches committed
+system.cpu.commit.COM:bw_lim_events 42336019 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
+system.cpu.commit.COM:committed_per_cycle::samples 1325593863 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean 1.289542 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev 1.917523 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0 632760901 47.73% 47.73% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1 317626873 23.96% 71.70% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2 153247647 11.56% 83.26% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3 83932703 6.33% 89.59% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4 35877325 2.71% 92.29% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5 27102905 2.04% 94.34% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6 13190001 1.00% 95.33% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7 19519489 1.47% 96.81% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8 42336019 3.19% 100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total 1325593863 # Number of insts commited each cycle
+system.cpu.commit.COM:count 1709408682 # Number of instructions committed
+system.cpu.commit.COM:loads 485926830 # Number of loads committed
+system.cpu.commit.COM:membars 0 # Number of memory barriers committed
+system.cpu.commit.COM:refs 660773875 # Number of memory references committed
+system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
+system.cpu.commit.branchMispredicts 33291323 # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 1709408682 # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls 333 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts 724671522 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 1709408682 # Number of Instructions Simulated
+system.cpu.committedInsts_total 1709408682 # Number of Instructions Simulated
+system.cpu.cpi 0.861505 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.861505 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 535355954 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 14975.678248 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11475.231071 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 527355564 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 119811266500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.014944 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 8000390 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 345154 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 87845602000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.014299 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 7655236 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 172586108 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 23783.327584 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20862.502653 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 168018197 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 108640123688 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.026467 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 4567911 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 2675787 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 39474441969 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.010963 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 1892124 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 3127.917167 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 19937.500000 # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 72.834141 # Average number of references to valid blocks.
+system.cpu.dcache.blocked::no_mshrs 25171 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs 78732803 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 159500 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 707942062 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 18176.791771 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 13335.628275 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 695373761 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 228451390188 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.017753 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 12568301 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 3020941 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 127320043969 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.013486 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 9547360 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0 0.997284 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 4084.873750 # Average occupied blocks per context
+system.cpu.dcache.overall_accesses 707942062 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 18176.791771 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 13335.628275 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 695373761 # number of overall hits
+system.cpu.dcache.overall_miss_latency 228451390188 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.017753 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 12568301 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 3020941 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 127320043969 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.013486 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 9547360 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.replacements 9543264 # number of replacements
+system.cpu.dcache.sampled_refs 9547360 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 4084.873750 # Cycle average of tags in use
+system.cpu.dcache.total_refs 695373761 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 7250730000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 3122652 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 107521017 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:DecodedInsts 2640561192 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 660508331 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 547645494 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 111598676 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:UnblockCycles 9919021 # Number of cycles decode is unblocking
+system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.inst_hits 0 # ITB inst hits
+system.cpu.dtb.inst_misses 0 # ITB inst misses
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.read_hits 0 # DTB read hits
+system.cpu.dtb.read_misses 0 # DTB read misses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.write_hits 0 # DTB write hits
+system.cpu.dtb.write_misses 0 # DTB write misses
+system.cpu.fetch.Branches 310539803 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 305341372 # Number of cache lines fetched
+system.cpu.fetch.Cycles 575112901 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 5844114 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 2356609774 # Number of instructions fetch has processed
+system.cpu.fetch.MiscStallCycles 3056047 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.SquashCycles 35765564 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.210869 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 305341372 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 251161589 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 1.600235 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples 1437192539 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.882507 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.825084 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 863142869 60.06% 60.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 76123612 5.30% 65.35% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 84397778 5.87% 71.23% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 62407182 4.34% 75.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 54486198 3.79% 79.36% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 66150908 4.60% 83.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 49722936 3.46% 87.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 19741369 1.37% 88.80% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 161019687 11.20% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 1437192539 # Number of instructions fetched each cycle (Total)
+system.cpu.icache.ReadReq_accesses 305341372 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 34138.917794 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 34194.369973 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 305340411 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 32807500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 961 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 215 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 25509000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 746 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 409303.500000 # Average number of references to valid blocks.
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 305341372 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 34138.917794 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 34194.369973 # average overall mshr miss latency
+system.cpu.icache.demand_hits 305340411 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 32807500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses
+system.cpu.icache.demand_misses 961 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 215 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 25509000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000002 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 746 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0 0.297244 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 608.756375 # Average occupied blocks per context
+system.cpu.icache.overall_accesses 305341372 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 34138.917794 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 34194.369973 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 305340411 # number of overall hits
+system.cpu.icache.overall_miss_latency 32807500 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses
+system.cpu.icache.overall_misses 961 # number of overall misses
+system.cpu.icache.overall_mshr_hits 215 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 25509000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000002 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 746 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.replacements 10 # number of replacements
+system.cpu.icache.sampled_refs 746 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 608.756375 # Cycle average of tags in use
+system.cpu.icache.total_refs 305340411 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idleCycles 35471905 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 234624640 # Number of branches executed
+system.cpu.iew.EXEC:nop 0 # number of nop insts executed
+system.cpu.iew.EXEC:rate 1.389966 # Inst execution rate
+system.cpu.iew.EXEC:refs 783869507 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 215578815 # Number of stores executed
+system.cpu.iew.EXEC:swp 0 # number of swp insts executed
+system.cpu.iew.WB:consumers 2289056926 # num instructions consuming a value
+system.cpu.iew.WB:count 2009251521 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.549566 # average fanout of values written-back
+system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.WB:producers 1257988693 # num instructions producing a value
+system.cpu.iew.WB:rate 1.364365 # insts written-back per cycle
+system.cpu.iew.WB:sent 2020755883 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 34959273 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 18898435 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 660629203 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 422 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 10495423 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 320206682 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 2433961539 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 568290692 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 53852412 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 2046953136 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 1105294 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu.iew.iewLSQFullEvents 81032 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 111598676 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 1881770 # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked 185278 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 29166049 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 474578 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.memOrderViolation 2909115 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 174702372 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 145359637 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 2909115 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 16680292 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 18278981 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 1.160759 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.160759 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntAlu 1282325001 61.04% 61.04% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntMult 1250884 0.06% 61.10% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 61.10% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.00% 61.10% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 61.10% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 61.10% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 61.10% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 61.10% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 61.10% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 61.10% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 61.10% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 61.10% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 61.10% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 61.10% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 61.10% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 61.10% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 61.10% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 61.10% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 61.10% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 61.10% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 61.10% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 61.10% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 61.10% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 20 0.00% 61.10% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 3 0.00% 61.10% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 17 0.00% 61.10% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 61.10% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 61.10% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 61.10% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemRead 577865457 27.51% 88.61% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemWrite 239364164 11.39% 100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::total 2100805548 # Type of FU issued
+system.cpu.iq.ISSUE:fu_busy_cnt 35252464 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.016780 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntAlu 38199 0.11% 0.11% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.11% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.11% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.11% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.11% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.11% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.11% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.11% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.11% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.11% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.11% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.11% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.11% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.11% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.11% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.11% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.11% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.11% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.11% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.11% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.11% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.11% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.11% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.11% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.11% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.11% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.11% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.11% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.11% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemRead 25515421 72.38% 72.49% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemWrite 9698844 27.51% 100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:issued_per_cycle::samples 1437192539 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::mean 1.461743 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.631414 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0 547476469 38.09% 38.09% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1 329329940 22.91% 61.01% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2 229433093 15.96% 76.97% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3 157481559 10.96% 87.93% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4 82220449 5.72% 93.65% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5 49053587 3.41% 97.06% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6 31255179 2.17% 99.24% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7 9054164 0.63% 99.87% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::8 1888099 0.13% 100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::total 1437192539 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate 1.426534 # Inst issue rate
+system.cpu.iq.iqInstsAdded 2433961117 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 2100805548 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 422 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 717692858 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 28325044 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 89 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 1287267033 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.inst_hits 0 # ITB inst hits
+system.cpu.itb.inst_misses 0 # ITB inst misses
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.l2cache.ReadExReq_accesses 1892128 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34475.157161 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31331.098502 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_hits 979531 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency 31461925000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 0.482313 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 912597 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 28592666500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.482313 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 912597 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 7655978 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34344.776594 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31123.973478 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 5633361 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 69466329000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.264188 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 2022617 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_miss_latency 62951535500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.264186 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 2022606 # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 3122652 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 3122652 # number of Writeback hits
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs 3948.352875 # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 2.651904 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked::no_mshrs 3582 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_mshrs 14143000 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 9548106 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34385.313643 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31188.371639 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 6612892 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 100928254000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.307413 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 2935214 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 11 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 91544202000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.307412 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 2935203 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0 0.494634 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.321250 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 16208.167153 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 10526.735069 # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses 9548106 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34385.313643 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31188.371639 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 6612892 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 100928254000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.307413 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 2935214 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 11 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 91544202000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.307412 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 2935203 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.replacements 2922772 # number of replacements
+system.cpu.l2cache.sampled_refs 2950094 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 26734.902222 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 7823366 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 156475359000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 1217059 # number of writebacks
+system.cpu.memDep0.conflictingLoads 102861524 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 93795307 # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads 660629203 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 320206682 # Number of stores inserted to the mem dependence unit.
+system.cpu.numCycles 1472664444 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 52825853 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps 1347252520 # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents 13396688 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 691140909 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 38063722 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents 9972 # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups 7136669468 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 2563712800 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 1945900239 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 526018927 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 111598676 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 55598501 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 598647716 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 9673 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 448 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 110186399 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 445 # count of temporary serializing insts renamed
+system.cpu.timesIdled 1109854 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.workload.PROG:num_syscalls 46 # Number of system calls
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=DerivO3CPU
+children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+cachePorts=200
+checker=Null
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=500
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+cpu_id=0
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+defer_registration=false
+dispatchWidth=8
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+issueToExecuteDelay=1
+issueWidth=8
+itb=system.cpu.itb
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+phase=0
+predType=tournament
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+smtCommitPolicy=RoundRobin
+smtFetchPolicy=SingleThread
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtNumFetchingThreads=1
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+squashWidth=8
+system=system
+tracer=system.cpu.tracer
+trapLatency=13
+wbDepth=1
+wbWidth=8
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
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+prefetch_degree=1
+prefetch_latency=10000
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+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=ArmTLB
+size=64
+
+[system.cpu.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+children=opList
+count=6
+opList=system.cpu.fuPool.FUList0.opList
+
+[system.cpu.fuPool.FUList0.opList]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntMult
+opLat=3
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+issueLat=19
+opClass=IntDiv
+opLat=20
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList4.opList
+
+[system.cpu.fuPool.FUList4.opList]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
+count=4
+opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+
+[system.cpu.fuPool.FUList5.opList00]
+type=OpDesc
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+opClass=SimdAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList01]
+type=OpDesc
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+opClass=SimdAddAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList02]
+type=OpDesc
+issueLat=1
+opClass=SimdAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList03]
+type=OpDesc
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+opLat=1
+
+[system.cpu.fuPool.FUList5.opList04]
+type=OpDesc
+issueLat=1
+opClass=SimdCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList05]
+type=OpDesc
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+opClass=SimdMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList06]
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+opClass=SimdMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList07]
+type=OpDesc
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+opClass=SimdMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList08]
+type=OpDesc
+issueLat=1
+opClass=SimdShift
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList09]
+type=OpDesc
+issueLat=1
+opClass=SimdShiftAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList10]
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+opLat=1
+
+[system.cpu.fuPool.FUList5.opList11]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAdd
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList12]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAlu
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList13]
+type=OpDesc
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+opClass=SimdFloatCmp
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList14]
+type=OpDesc
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+opClass=SimdFloatCvt
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList15]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatDiv
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList16]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMisc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList17]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMult
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList18]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMultAcc
+opLat=1
+
+[system.cpu.fuPool.FUList5.opList19]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatSqrt
+opLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+children=opList
+count=0
+opList=system.cpu.fuPool.FUList6.opList
+
+[system.cpu.fuPool.FUList6.opList]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList7.opList1]
+type=OpDesc
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+opLat=1
+
+[system.cpu.fuPool.FUList8]
+type=FUDesc
+children=opList
+count=1
+opList=system.cpu.fuPool.FUList8.opList
+
+[system.cpu.fuPool.FUList8.opList]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=20
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=ArmTLB
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+latency=1000
+max_miss_count=0
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+prefetch_data_accesses_only=false
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+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=twolf smred
+cwd=build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/twolf
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[0]
+
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
+hack: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jan 11 2011 18:16:01
+M5 revision b39a8457b332 7816 default ext/o3_regressions.patch qtip tip
+M5 started Jan 12 2011 04:18:31
+M5 executing on u200439-lin.austin.arm.com
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing
+Couldn't unlink build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing/smred.sav
+Couldn't unlink build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing/smred.sv2
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+
+TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
+Standard Cell Placement and Global Routing Program
+Authors: Carl Sechen, Bill Swartz
+ Yale University
+info: Increasing stack size by one page.
+ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
+ 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
+ 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
+ 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
+ 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
+ 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
+ 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
+106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
+122 123 124 Exiting @ tick 149819218000 because target called exit()
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 96216 # Simulator instruction rate (inst/s)
+host_mem_usage 255460 # Number of bytes of host memory used
+host_seconds 1920.75 # Real time elapsed on the host
+host_tick_rate 78000522 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 184806751 # Number of instructions simulated
+sim_seconds 0.149819 # Number of seconds simulated
+sim_ticks 149819218000 # Number of ticks simulated
+system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.BTBHits 51777441 # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 55728819 # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect 12604932 # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted 57019634 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 57019634 # Number of BP lookups
+system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
+system.cpu.commit.COM:branches 39499925 # Number of branches committed
+system.cpu.commit.COM:bw_lim_events 586569 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
+system.cpu.commit.COM:committed_per_cycle::samples 285162307 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean 0.648076 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev 0.934649 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0 151202157 53.02% 53.02% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1 102481067 35.94% 88.96% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2 22788720 7.99% 96.95% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3 3864440 1.36% 98.31% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4 2118453 0.74% 99.05% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5 1126211 0.39% 99.45% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6 605325 0.21% 99.66% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7 389365 0.14% 99.79% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8 586569 0.21% 100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total 285162307 # Number of insts commited each cycle
+system.cpu.commit.COM:count 184806751 # Number of instructions committed
+system.cpu.commit.COM:loads 29554611 # Number of loads committed
+system.cpu.commit.COM:membars 0 # Number of memory barriers committed
+system.cpu.commit.COM:refs 42081439 # Number of memory references committed
+system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
+system.cpu.commit.branchMispredicts 12955642 # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 184806751 # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls 1569953 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts 36913939 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 184806751 # Number of Instructions Simulated
+system.cpu.committedInsts_total 184806751 # Number of Instructions Simulated
+system.cpu.cpi 1.621361 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.621361 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 32436972 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 31572.372561 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32361.760660 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 32435383 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 50168500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.000049 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 1589 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 862 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 23527000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 727 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 12273971 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 25387.973098 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35046.203111 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 12266388 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 192517000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.000618 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 7583 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 6490 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 38305500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.000089 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 1093 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 9000 # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 24561.412637 # Average number of references to valid blocks.
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 9000 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 44710943 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 26459.387266 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 33973.901099 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 44701771 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 242685500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.000205 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 9172 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 7352 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 61832500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.000041 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 1820 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0 0.337576 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 1382.712740 # Average occupied blocks per context
+system.cpu.dcache.overall_accesses 44710943 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 26459.387266 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 33973.901099 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 44701771 # number of overall hits
+system.cpu.dcache.overall_miss_latency 242685500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.000205 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 9172 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 7352 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 61832500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.000041 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 1820 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.replacements 46 # number of replacements
+system.cpu.dcache.sampled_refs 1820 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 1382.712740 # Cycle average of tags in use
+system.cpu.dcache.total_refs 44701771 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 17 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 21645695 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:DecodedInsts 264148403 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 61114586 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 200863194 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 14404012 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:UnblockCycles 1538832 # Number of cycles decode is unblocking
+system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.inst_hits 0 # ITB inst hits
+system.cpu.dtb.inst_misses 0 # ITB inst misses
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.read_hits 0 # DTB read hits
+system.cpu.dtb.read_misses 0 # DTB read misses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.write_hits 0 # DTB write hits
+system.cpu.dtb.write_misses 0 # DTB write misses
+system.cpu.fetch.Branches 57019634 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 24416320 # Number of cache lines fetched
+system.cpu.fetch.Cycles 213842486 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 1112165 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 254182972 # Number of instructions fetch has processed
+system.cpu.fetch.MiscStallCycles 47170 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.SquashCycles 13195953 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.190295 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 24416320 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 51777441 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 0.848299 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples 299566319 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.927729 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 1.045167 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 86216737 28.78% 28.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 186583672 62.28% 91.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 11093729 3.70% 94.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 7887786 2.63% 97.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 1768857 0.59% 97.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 2263080 0.76% 98.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 1007502 0.34% 99.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 913678 0.31% 99.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 1831278 0.61% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 299566319 # Number of instructions fetched each cycle (Total)
+system.cpu.icache.ReadReq_accesses 24416320 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 25129.997165 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 21979.962430 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 24412793 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 88633500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000144 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 3527 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 333 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 70204000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000131 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 3194 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 7643.329054 # Average number of references to valid blocks.
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 24416320 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 25129.997165 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 21979.962430 # average overall mshr miss latency
+system.cpu.icache.demand_hits 24412793 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 88633500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000144 # miss rate for demand accesses
+system.cpu.icache.demand_misses 3527 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 333 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 70204000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000131 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 3194 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0 0.617996 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 1265.656539 # Average occupied blocks per context
+system.cpu.icache.overall_accesses 24416320 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 25129.997165 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 21979.962430 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 24412793 # number of overall hits
+system.cpu.icache.overall_miss_latency 88633500 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000144 # miss rate for overall accesses
+system.cpu.icache.overall_misses 3527 # number of overall misses
+system.cpu.icache.overall_mshr_hits 333 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 70204000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000131 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 3194 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.replacements 1539 # number of replacements
+system.cpu.icache.sampled_refs 3194 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 1265.656539 # Cycle average of tags in use
+system.cpu.icache.total_refs 24412793 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idleCycles 72118 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 40333139 # Number of branches executed
+system.cpu.iew.EXEC:nop 0 # number of nop insts executed
+system.cpu.iew.EXEC:rate 0.675496 # Inst execution rate
+system.cpu.iew.EXEC:refs 46706722 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 12922741 # Number of stores executed
+system.cpu.iew.EXEC:swp 0 # number of swp insts executed
+system.cpu.iew.WB:consumers 166977315 # num instructions consuming a value
+system.cpu.iew.WB:count 199490949 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.694920 # average fanout of values written-back
+system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.WB:producers 116035924 # num instructions producing a value
+system.cpu.iew.WB:rate 0.665772 # insts written-back per cycle
+system.cpu.iew.WB:sent 200460633 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 13076729 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 1256 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 37075609 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 1668755 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 11833620 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 14988552 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 221729697 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 33783981 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 10734422 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 202404420 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 14404012 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 103 # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 638748 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 2434 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.memOrderViolation 295230 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 7520997 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 2461724 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 295230 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 1407561 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 11669168 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 0.616766 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.616766 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntAlu 163249340 76.59% 76.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntMult 907348 0.43% 77.02% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 77.02% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 77.02% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 77.02% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 77.02% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 77.02% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 77.02% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 77.02% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAdd 16007 0.01% 77.03% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 77.03% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 77.03% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 77.03% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 77.03% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 77.03% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 77.03% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 77.03% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 77.03% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 77.03% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 77.03% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 33154 0.02% 77.04% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 77.04% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 157340 0.07% 77.12% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 265597 0.12% 77.24% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 74720 0.04% 77.28% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 439795 0.21% 77.48% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 197622 0.09% 77.57% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 71713 0.03% 77.61% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 318 0.00% 77.61% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemRead 34601051 16.23% 93.84% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemWrite 13124837 6.16% 100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::total 213138842 # Type of FU issued
+system.cpu.iq.ISSUE:fu_busy_cnt 1172618 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.005502 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntAlu 53 0.00% 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemRead 789273 67.31% 67.31% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemWrite 383292 32.69% 100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:issued_per_cycle::samples 299566319 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::mean 0.711491 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::stdev 0.811323 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0 130437800 43.54% 43.54% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1 140705247 46.97% 90.51% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2 18781279 6.27% 96.78% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3 5495734 1.83% 98.62% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4 2758024 0.92% 99.54% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5 1051071 0.35% 99.89% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6 286459 0.10% 99.98% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7 28010 0.01% 99.99% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::8 22695 0.01% 100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::total 299566319 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate 0.711320 # Inst issue rate
+system.cpu.iq.iqInstsAdded 220060942 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 213138842 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 1668755 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 20677309 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 250153 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 98802 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 37784077 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.inst_hits 0 # ITB inst hits
+system.cpu.itb.inst_misses 0 # ITB inst misses
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.l2cache.ReadExReq_accesses 1093 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34262.672811 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31130.875576 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_hits 8 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency 37175000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 0.992681 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 1085 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 33777000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.992681 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 1085 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 3921 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34264.029618 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31081.500393 # average ReadReq mshr miss latency
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+system.cpu.l2cache.ReadReq_miss_latency 87921500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.654425 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 2566 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_hits 20 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_miss_latency 79133500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.649324 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 2546 # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 17 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 17 # number of Writeback hits
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 0.530333 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 5014 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34263.626404 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31096.254475 # average overall mshr miss latency
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+system.cpu.l2cache.demand_miss_latency 125096500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.728161 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 3651 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 20 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 112910500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.724172 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 3631 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0 0.055506 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.000152 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 1818.805023 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 4.996217 # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses 5014 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34263.626404 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31096.254475 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 1363 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 125096500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.728161 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 3651 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 20 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 112910500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.724172 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 3631 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.replacements 0 # number of replacements
+system.cpu.l2cache.sampled_refs 2555 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 1823.801240 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 1355 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 0 # number of writebacks
+system.cpu.memDep0.conflictingLoads 3889323 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 2640936 # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads 37075609 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 14988552 # Number of stores inserted to the mem dependence unit.
+system.cpu.numCycles 299638437 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 3074 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps 178683528 # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents 2322 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 73277760 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 19202 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:RenameLookups 601080290 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 249997565 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 249829292 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 190277990 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 14404012 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 1750038 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 71145762 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 19853445 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 2086015 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 2928694 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 1863087 # count of temporary serializing insts renamed
+system.cpu.timesIdled 1363 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.workload.PROG:num_syscalls 400 # Number of system calls
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
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+mem_mode=atomic
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+
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+
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+
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+type=ArmTLB
+size=64
+
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+
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+
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+
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+
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+
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+count=4
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+
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+
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+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=hello
+cwd=
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/chips/pd/randd/dist/test-progs/hello/bin/arm/linux/hello
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[0]
+
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
+hack: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Jan 11 2011 18:16:01
+M5 revision b39a8457b332 7816 default ext/o3_regressions.patch qtip tip
+M5 started Jan 12 2011 04:32:17
+M5 executing on u200439-lin.austin.arm.com
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+Hello world!
+Exiting @ tick 10317500 because target called exit()
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 59213 # Simulator instruction rate (inst/s)
+host_mem_usage 247916 # Number of bytes of host memory used
+host_seconds 0.10 # Real time elapsed on the host
+host_tick_rate 108401013 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 5620 # Number of instructions simulated
+sim_seconds 0.000010 # Number of seconds simulated
+sim_ticks 10317500 # Number of ticks simulated
+system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.BTBHits 790 # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 2144 # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect 348 # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted 2189 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 2189 # Number of BP lookups
+system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
+system.cpu.commit.COM:branches 840 # Number of branches committed
+system.cpu.commit.COM:bw_lim_events 69 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
+system.cpu.commit.COM:committed_per_cycle::samples 10656 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean 0.527402 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev 1.275771 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0 8217 77.11% 77.11% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1 1132 10.62% 87.73% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2 525 4.93% 92.66% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3 313 2.94% 95.60% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4 174 1.63% 97.23% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5 143 1.34% 98.57% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6 45 0.42% 99.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7 38 0.36% 99.35% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8 69 0.65% 100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total 10656 # Number of insts commited each cycle
+system.cpu.commit.COM:count 5620 # Number of instructions committed
+system.cpu.commit.COM:loads 1207 # Number of loads committed
+system.cpu.commit.COM:membars 0 # Number of memory barriers committed
+system.cpu.commit.COM:refs 2145 # Number of memory references committed
+system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
+system.cpu.commit.branchMispredicts 548 # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 5620 # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls 1 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts 6019 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 5620 # Number of Instructions Simulated
+system.cpu.committedInsts_total 5620 # Number of Instructions Simulated
+system.cpu.cpi 3.671886 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 3.671886 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 1812 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 32038.043478 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 29730.088496 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 1628 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 5895000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.101545 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 184 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 71 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 3359500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.062362 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 113 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 924 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 35706.185567 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36109.756098 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 633 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 10390500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.314935 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 291 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 250 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 1480500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.044372 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 41 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 14.681818 # Average number of references to valid blocks.
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 2736 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 34285.263158 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 31428.571429 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 2261 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 16285500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.173611 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 475 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 321 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 4840000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.056287 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 154 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0 0.022828 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 93.502986 # Average occupied blocks per context
+system.cpu.dcache.overall_accesses 2736 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 34285.263158 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 31428.571429 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 2261 # number of overall hits
+system.cpu.dcache.overall_miss_latency 16285500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.173611 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 475 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 321 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 4840000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.056287 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 154 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.replacements 0 # number of replacements
+system.cpu.dcache.sampled_refs 154 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 93.502986 # Cycle average of tags in use
+system.cpu.dcache.total_refs 2261 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 0 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 805 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:DecodedInsts 14956 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 7320 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 2481 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 1162 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:UnblockCycles 50 # Number of cycles decode is unblocking
+system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.inst_hits 0 # ITB inst hits
+system.cpu.dtb.inst_misses 0 # ITB inst misses
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.read_hits 0 # DTB read hits
+system.cpu.dtb.read_misses 0 # DTB read misses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.write_hits 0 # DTB write hits
+system.cpu.dtb.write_misses 0 # DTB write misses
+system.cpu.fetch.Branches 2189 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 1675 # Number of cache lines fetched
+system.cpu.fetch.Cycles 2612 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 323 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 12619 # Number of instructions fetch has processed
+system.cpu.fetch.MiscStallCycles 44 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.SquashCycles 583 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.106077 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 1675 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 790 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 0.611504 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples 11818 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.321713 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.741660 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 9206 77.90% 77.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 206 1.74% 79.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 151 1.28% 80.92% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 211 1.79% 82.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 193 1.63% 84.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 242 2.05% 86.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 136 1.15% 87.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 103 0.87% 88.41% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 1370 11.59% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 11818 # Number of instructions fetched each cycle (Total)
+system.cpu.icache.ReadReq_accesses 1675 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 34635.549872 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 33596.573209 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 1284 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 13542500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.233433 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 391 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 70 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 10784500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.191642 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 4 # Average number of references to valid blocks.
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 1675 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 34635.549872 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 33596.573209 # average overall mshr miss latency
+system.cpu.icache.demand_hits 1284 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 13542500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.233433 # miss rate for demand accesses
+system.cpu.icache.demand_misses 391 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 70 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 10784500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.191642 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0 0.079518 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 162.851965 # Average occupied blocks per context
+system.cpu.icache.overall_accesses 1675 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 34635.549872 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 33596.573209 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 1284 # number of overall hits
+system.cpu.icache.overall_miss_latency 13542500 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.233433 # miss rate for overall accesses
+system.cpu.icache.overall_misses 391 # number of overall misses
+system.cpu.icache.overall_mshr_hits 70 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 10784500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.191642 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.replacements 5 # number of replacements
+system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 162.851965 # Cycle average of tags in use
+system.cpu.icache.total_refs 1284 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idleCycles 8818 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 1306 # Number of branches executed
+system.cpu.iew.EXEC:nop 0 # number of nop insts executed
+system.cpu.iew.EXEC:rate 0.417184 # Inst execution rate
+system.cpu.iew.EXEC:refs 3129 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 1169 # Number of stores executed
+system.cpu.iew.EXEC:swp 0 # number of swp insts executed
+system.cpu.iew.WB:consumers 7928 # num instructions consuming a value
+system.cpu.iew.WB:count 7988 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.467709 # average fanout of values written-back
+system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.WB:producers 3708 # num instructions producing a value
+system.cpu.iew.WB:rate 0.387091 # insts written-back per cycle
+system.cpu.iew.WB:sent 8290 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 642 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 230 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 2545 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 2 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 596 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 1646 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 11906 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 1960 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 475 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 8609 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 20 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 1162 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 28 # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 59 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.memOrderViolation 34 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 2 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 1338 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 708 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 34 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 609 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 33 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 0.272340 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.272340 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntAlu 5717 62.93% 62.93% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntMult 5 0.06% 62.99% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.99% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 62.99% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 62.99% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 62.99% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 62.99% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 62.99% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 62.99% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 62.99% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 62.99% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 62.99% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 62.99% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 62.99% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 62.99% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 62.99% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 62.99% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 62.99% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 62.99% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 62.99% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 62.99% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 62.99% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 62.99% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 62.99% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 62.99% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 3 0.03% 63.02% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 63.02% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 63.02% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 63.02% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemRead 2133 23.48% 86.50% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemWrite 1226 13.50% 100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::total 9084 # Type of FU issued
+system.cpu.iq.ISSUE:fu_busy_cnt 181 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.019925 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntAlu 4 2.21% 2.21% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.21% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.21% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.21% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.21% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.21% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.21% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.21% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.21% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.21% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.21% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.21% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.21% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.21% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.21% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.21% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.21% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.21% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.21% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.21% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.21% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.21% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.21% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.21% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.21% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.21% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.21% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.21% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.21% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemRead 109 60.22% 62.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemWrite 68 37.57% 100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:issued_per_cycle::samples 11818 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::mean 0.768658 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.451524 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0 8185 69.26% 69.26% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1 1366 11.56% 80.82% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2 758 6.41% 87.23% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3 566 4.79% 92.02% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4 474 4.01% 96.03% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5 284 2.40% 98.43% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6 122 1.03% 99.47% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7 48 0.41% 99.87% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::8 15 0.13% 100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::total 11818 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate 0.440202 # Inst issue rate
+system.cpu.iq.iqInstsAdded 11904 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 9084 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 2 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 5957 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 59 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 10171 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.inst_hits 0 # ITB inst hits
+system.cpu.itb.inst_misses 0 # ITB inst misses
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.l2cache.ReadExReq_accesses 41 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34500 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31365.853659 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 1414500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 41 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 1286000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 41 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 434 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34308.860759 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31166.666667 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 39 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 13552000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.910138 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 395 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_miss_latency 11968000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.884793 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 384 # number of ReadReq MSHR misses
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 0.101562 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 475 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34326.834862 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31185.882353 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 39 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 14966500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.917895 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 436 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 11 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 13254000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.894737 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 425 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0 0.006167 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 202.074939 # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses 475 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34326.834862 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31185.882353 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 39 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 14966500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.917895 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 436 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 11 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 13254000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.894737 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 425 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.replacements 0 # number of replacements
+system.cpu.l2cache.sampled_refs 384 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 202.074939 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 39 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 0 # number of writebacks
+system.cpu.memDep0.conflictingLoads 12 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 11 # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads 2545 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1646 # Number of stores inserted to the mem dependence unit.
+system.cpu.numCycles 20636 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 346 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps 4006 # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents 46 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 7538 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 123 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:RenameLookups 37508 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 13960 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 10094 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 2314 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 1162 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 187 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 6085 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 271 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 4 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 537 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 1 # count of temporary serializing insts renamed
+system.cpu.timesIdled 180 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.workload.PROG:num_syscalls 13 # Number of system calls
+
+---------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache dtb icache itb l2cache toL2Bus tracer workload
+checker=Null
+clock=500
+cpu_id=0
+defer_registration=false
+do_checkpoint_insts=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=262144
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.dtb]
+type=ArmTLB
+size=64
+
+[system.cpu.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+latency=1000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=131072
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.itb]
+type=ArmTLB
+size=64
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=2
+block_size=64
+forward_snoops=true
+hash_delay=1
+latency=10000
+max_miss_count=0
+mshrs=10
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=2097152
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
+
+[system.cpu.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=hello
+cwd=
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/chips/pd/randd/dist/test-progs/hello/bin/arm/linux/hello
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=1000
+header_cycles=1
+use_default_range=false
+width=64
+port=system.physmem.port[0] system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[0]
+
--- /dev/null
+warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
+hack: be nice to actually delete the event here
--- /dev/null
+M5 Simulator System
+
+Copyright (c) 2001-2008
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Dec 7 2010 18:51:32
+M5 revision 331c8c76d885 7806 default qtip tip ext/mismatched_new_delete.patch
+M5 started Dec 7 2010 18:51:46
+M5 executing on u200439-lin.austin.arm.com
+command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+Hello world!
+Exiting @ tick 26346000 because target called exit()
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 315416 # Simulator instruction rate (inst/s)
+host_mem_usage 248988 # Number of bytes of host memory used
+host_seconds 0.02 # Real time elapsed on the host
+host_tick_rate 1472008046 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 5563 # Number of instructions simulated
+sim_seconds 0.000026 # Number of seconds simulated
+sim_ticks 26346000 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses 1164 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 48787.878788 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 45787.878788 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 1065 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 4830000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.085052 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 99 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 4533000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.085052 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 99 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 924 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 881 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 2408000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.046537 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 43 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 2279000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.046537 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 43 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 13.704225 # Average number of references to valid blocks.
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 2088 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 50971.830986 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 47971.830986 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 1946 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 7238000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.068008 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 142 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 6812000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.068008 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 142 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0 0.020405 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 83.579331 # Average occupied blocks per context
+system.cpu.dcache.overall_accesses 2088 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 50971.830986 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 47971.830986 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 1946 # number of overall hits
+system.cpu.dcache.overall_miss_latency 7238000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.068008 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 142 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 6812000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.068008 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 142 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.replacements 0 # number of replacements
+system.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 83.579331 # Cycle average of tags in use
+system.cpu.dcache.total_refs 1946 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 0 # number of writebacks
+system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.inst_accesses 0 # ITB inst accesses
+system.cpu.dtb.inst_hits 0 # ITB inst hits
+system.cpu.dtb.inst_misses 0 # ITB inst misses
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.read_hits 0 # DTB read hits
+system.cpu.dtb.read_misses 0 # DTB read misses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.write_hits 0 # DTB write hits
+system.cpu.dtb.write_misses 0 # DTB write misses
+system.cpu.icache.ReadReq_accesses 4580 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 53211.618257 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 50211.618257 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 4339 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 12824000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.052620 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 241 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 12101000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.052620 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 241 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 18.004149 # Average number of references to valid blocks.
+system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 4580 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 53211.618257 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 50211.618257 # average overall mshr miss latency
+system.cpu.icache.demand_hits 4339 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 12824000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.052620 # miss rate for demand accesses
+system.cpu.icache.demand_misses 241 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 12101000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.052620 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 241 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0 0.055892 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 114.467059 # Average occupied blocks per context
+system.cpu.icache.overall_accesses 4580 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 53211.618257 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 50211.618257 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 4339 # number of overall hits
+system.cpu.icache.overall_miss_latency 12824000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.052620 # miss rate for overall accesses
+system.cpu.icache.overall_misses 241 # number of overall misses
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 12101000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.052620 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 241 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.replacements 1 # number of replacements
+system.cpu.icache.sampled_refs 241 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 114.467059 # Cycle average of tags in use
+system.cpu.icache.total_refs 4339 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
+system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
+system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.inst_accesses 0 # ITB inst accesses
+system.cpu.itb.inst_hits 0 # ITB inst hits
+system.cpu.itb.inst_misses 0 # ITB inst misses
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.l2cache.ReadExReq_accesses 43 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 2236000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 43 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 1720000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 43 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 340 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 33 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 15964000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.902941 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 307 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 12280000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.902941 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 307 # number of ReadReq MSHR misses
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 0.107492 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 383 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 33 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 18200000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.913838 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 350 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 14000000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.913838 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 350 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0 0.004696 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 153.883328 # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses 383 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 33 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 18200000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.913838 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 350 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 14000000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.913838 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 350 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.replacements 0 # number of replacements
+system.cpu.l2cache.sampled_refs 307 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 153.883328 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 33 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 0 # number of writebacks
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 52692 # number of cpu cycles simulated
+system.cpu.num_insts 5563 # Number of instructions executed
+system.cpu.num_refs 2145 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 13 # Number of system calls
+
+---------- End Simulation Statistics ----------
projects / gem5.git / commitdiff