Added ice40 SB_CARRY support

diff --git a/techlibs/ice40/Makefile.inc b/techlibs/ice40/Makefile.inc
index 6e556ab888fe0f426b592ea10ab7229ded568ed5..cd178d66450f0dc20d936c7b701328bfd9a897db 100644 (file)
--- a/techlibs/ice40/Makefile.inc
+++ b/techlibs/ice40/Makefile.inc
@@ -2,6 +2,7 @@
 OBJS += techlibs/ice40/synth_ice40.o
 OBJS += techlibs/ice40/ice40_ffssr.o
 
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/arith_map.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_map.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_sim.v))
 

diff --git a/techlibs/ice40/arith_map.v b/techlibs/ice40/arith_map.v
new file mode 100644 (file)
index 0000000..b0f66a2
--- /dev/null
+++ b/techlibs/ice40/arith_map.v
@@ -0,0 +1,70 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *  
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *  
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+(* techmap_celltype = "$alu" *)
+module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
+       parameter A_SIGNED = 0;
+       parameter B_SIGNED = 0;
+       parameter A_WIDTH = 1;
+       parameter B_WIDTH = 1;
+       parameter Y_WIDTH = 1;
+
+       input [A_WIDTH-1:0] A;
+       input [B_WIDTH-1:0] B;
+       output [Y_WIDTH-1:0] X, Y;
+
+       input CI, BI;
+       output [Y_WIDTH-1:0] CO;
+
+       wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
+
+       wire [Y_WIDTH-1:0] A_buf, B_buf;
+       \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
+       \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+
+       wire [Y_WIDTH-1:0] AA = A_buf;
+       wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
+       wire [Y_WIDTH-1:0] C = {CO, CI};
+
+       genvar i;
+       generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
+               SB_CARRY carry (
+                       .I0(AA[i]),
+                       .I1(BB[i]),
+                       .CI(C[i]),
+                       .CO(CO[i])
+               );
+               SB_LUT4 #(
+                       //         I0: 1010 1010 1010 1010
+                       //         I1: 1100 1100 1100 1100
+                       //         I2: 1111 0000 1111 0000
+                       //         I3: 1111 1111 0000 0000
+                       .LUT_INIT(16'b 0110_1001_1001_0110)
+               ) adder (
+                       .I0(1'b0),
+                       .I1(AA[i]),
+                       .I2(BB[i]),
+                       .I3(C[i]),
+                       .O(Y[i])
+               );
+       end endgenerate
+
+       assign X = AA ^ BB;
+endmodule
+

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 1d23cd954e03ea2edb99b159a0db9b2e3087c0a5..dff12f8a9fbda978dc8d8a3be83c823883b533ec 100644 (file)
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -66,7 +66,7 @@ struct SynthIce40Pass : public Pass {
                log("        opt -fast -mux_undef -undriven -fine\n");
                log("        memory_map\n");
                log("        opt -undriven -fine\n");
-               log("        techmap\n");
+               log("        techmap -map +/techmap.v -map +/ice40/arith_map.v\n");
                log("        opt -fast\n");
                log("\n");
                log("    map_ffs:\n");
@@ -95,6 +95,7 @@ struct SynthIce40Pass : public Pass {
        {
                std::string top_opt = "-auto-top";
                std::string run_from, run_to;
+               bool nocarry = false;
 
                size_t argidx;
                for (argidx = 1; argidx < args.size(); argidx++)
@@ -111,6 +112,10 @@ struct SynthIce40Pass : public Pass {
                                run_to = args[argidx].substr(pos+1);
                                continue;
                        }
+                       if (args[argidx] == "-nocarry") {
+                               nocarry = true;
+                               continue;
+                       }
                        break;
                }
                extra_args(args, argidx, design);
@@ -139,7 +144,10 @@ struct SynthIce40Pass : public Pass {
                        Pass::call(design, "opt -fast -mux_undef -undriven -fine");
                        Pass::call(design, "memory_map");
                        Pass::call(design, "opt -undriven -fine");
-                       Pass::call(design, "techmap");
+                       if (nocarry)
+                               Pass::call(design, "techmap");
+                       else
+                               Pass::call(design, "techmap -map +/techmap.v -map +/ice40/arith_map.v");
                        Pass::call(design, "opt -fast");
                }