We should trigger an Undefined Instruction if those registers
are accessed in non-secure mode
Change-Id: I45ec01e9e4ae9a38d59e56a51e198b4199a7d814
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37616
Tested-by: kokoro <noreply+kokoro@google.com>
.hyp().mon()
.mapsTo(MISCREG_VTCR);
InitReg(MISCREG_VSTTBR_EL2)
- .hyp().mon();
+ .hypSecure().mon();
InitReg(MISCREG_VSTCR_EL2)
- .hyp().mon();
+ .hypSecure().mon();
InitReg(MISCREG_TTBR0_EL3)
.mon();
InitReg(MISCREG_TCR_EL3)