re PR rtl-optimization/83628 (performance regression when accessing arrays on alpha)

	PR target/83628
	* config/alpha/alpha.md (*saddsi_1): New insn_ans_split pattern.
	(*saddl_se_1): Ditto.
	(*ssubsi_1): Ditto.
	(*saddl_se_1): Ditto.

testsuite/ChangeLog:

	PR target/83628
	* gcc.target/alpha/pr83628-3.c: New test.

From-SVN: r256589

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 752c77731e21abd91df22083d18f75ced3d9811b..05cc049abc49a3c0593ac1297d75875ab3863f50 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2018-01-12  Uros Bizjak  <ubizjak@gmail.com>
+
+       PR target/83628
+       * config/alpha/alpha.md (*saddsi_1): New insn_ans_split pattern.
+       (*saddl_se_1): Ditto.
+       (*ssubsi_1): Ditto.
+       (*saddl_se_1): Ditto.
+
 2018-01-12  Richard Sandiford  <richard.sandiford@linaro.org>
 
        * tree-predcom.c (aff_combination_dr_offset): Use wi::to_poly_widest

diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md
index 7493f3e9d3510124212e3c4628176a6639a89a68..5d82e5a4adf73d08e0a186d63d2419715340f5f4 100644 (file)
--- a/gcc/config/alpha/alpha.md
+++ b/gcc/config/alpha/alpha.md
@@ -527,17 +527,50 @@
    s%P2add<modesuffix> %1,%3,%0
    s%P2sub<modesuffix> %1,%n3,%0")
 
+(define_insn_and_split "*saddsi_1"
+  [(set (match_operand:SI 0 "register_operand" "=r,r")
+       (plus:SI
+        (subreg:SI
+         (ashift:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r")
+                    (match_operand:DI 2 "const23_operand" "I,I")) 0)
+        (match_operand:SI 3 "sext_add_operand" "rI,O")))]
+  ""
+  "#"
+  ""
+  [(set (match_dup 0)
+       (plus:SI (ashift:SI (match_dup 1) (match_dup 2))
+                (match_dup 3)))]
+  "operands[1] = gen_lowpart (SImode, operands[1]);")
+
 (define_insn "*saddl_se"
   [(set (match_operand:DI 0 "register_operand" "=r,r")
        (sign_extend:DI
-        (plus:SI (ashift:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
-                            (match_operand:SI 2 "const23_operand" "I,I"))
-                 (match_operand:SI 3 "sext_add_operand" "rI,O"))))]
+        (plus:SI
+         (ashift:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
+                    (match_operand:SI 2 "const23_operand" "I,I"))
+        (match_operand:SI 3 "sext_add_operand" "rI,O"))))]
   ""
   "@
    s%P2addl %1,%3,%0
    s%P2subl %1,%n3,%0")
 
+(define_insn_and_split "*saddl_se_1"
+  [(set (match_operand:DI 0 "register_operand" "=r,r")
+       (sign_extend:DI
+        (plus:SI
+         (subreg:SI
+          (ashift:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r")
+                     (match_operand:DI 2 "const23_operand" "I,I")) 0)
+        (match_operand:SI 3 "sext_add_operand" "rI,O"))))]
+  ""
+  "#"
+  ""
+  [(set (match_dup 0)
+       (sign_extend:DI
+        (plus:SI (ashift:SI (match_dup 1) (match_dup 2))
+                 (match_dup 3))))]
+  "operands[1] = gen_lowpart (SImode, operands[1]);")
+
 (define_split
   [(set (match_operand:DI 0 "register_operand")
        (sign_extend:DI
@@ -627,15 +660,48 @@
   ""
   "s%P2sub<modesuffix> %1,%3,%0")
 
+(define_insn_and_split "*ssubsi_1"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+       (minus:SI
+        (subreg:SI
+         (ashift:DI (match_operand:DI 1 "reg_not_elim_operand" "r")
+                    (match_operand:DI 2 "const23_operand" "I")) 0)
+        (match_operand:SI 3 "reg_or_8bit_operand" "rI")))]
+  ""
+  "#"
+  ""
+  [(set (match_dup 0)
+       (minus:SI (ashift:SI (match_dup 1) (match_dup 2))
+                 (match_dup 3)))]
+  "operands[1] = gen_lowpart (SImode, operands[1]);")
+
 (define_insn "*ssubl_se"
   [(set (match_operand:DI 0 "register_operand" "=r")
        (sign_extend:DI
-        (minus:SI (ashift:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
-                             (match_operand:SI 2 "const23_operand" "I"))
-                  (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
+        (minus:SI
+         (ashift:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
+                    (match_operand:SI 2 "const23_operand" "I"))
+        (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
   ""
   "s%P2subl %1,%3,%0")
 
+(define_insn_and_split "*ssubl_se_1"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+       (sign_extend:DI
+        (minus:SI
+         (subreg:SI
+          (ashift:DI (match_operand:DI 1 "reg_not_elim_operand" "r")
+                     (match_operand:DI 2 "const23_operand" "I")) 0)
+        (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
+  ""
+  "#"
+  ""
+  [(set (match_dup 0)
+       (sign_extend:DI
+        (minus:SI (ashift:SI (match_dup 1) (match_dup 2))
+                  (match_dup 3))))]
+  "operands[1] = gen_lowpart (SImode, operands[1]);")
+
 (define_insn "subv<mode>3"
   [(set (match_operand:I48MODE 0 "register_operand" "=r")
        (minus:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "rJ")
@@ -1200,7 +1266,7 @@
         (subreg:SI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
                               (match_operand:DI 2 "const_int_operand" "P"))
                    0)))]
-  "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3"
+  "IN_RANGE (INTVAL (operands[2]), 1, 3)"
 {
   if (operands[2] == const1_rtx)
     return "addl %r1,%r1,%0";

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index e9617740193ab00546b19d2f5920332c41f09ce9..64e14f283d575874e7e9c93d293c7d695803c477 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2018-01-12  Uros Bizjak  <ubizjak@gmail.com>
+
+       PR target/83628
+       * gcc.target/alpha/pr83628-3.c: New test.
+
 2018-01-12  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
 
        * lib/target-supports.exp (check_effective_target_avx512f): Also

diff --git a/gcc/testsuite/gcc.target/alpha/pr83628-2.c b/gcc/testsuite/gcc.target/alpha/pr83628-2.c
index 0910d38be00df8afb4d6fcf0ffe35a57fca45cd7..2f02181d28b21df3b24aa4cb955b70d10854767d 100644 (file)
--- a/gcc/testsuite/gcc.target/alpha/pr83628-2.c
+++ b/gcc/testsuite/gcc.target/alpha/pr83628-2.c
@@ -5,25 +5,25 @@
 int
 s4l (int a, int b)
 {
-  return a + b * 4;
+  return a * 4 + b;
 }
 
 int
 s8l (int a, int b)
 {
-  return a + b * 8;
+  return a * 8 + b;
 }
 
 long
 s4q (long a, long b)
 {
-  return a + b * 4;
+  return a * 4 + b;
 }
 
 long
 s8q (long a, long b)
 {
-  return a + b * 8;
+  return a * 8 + b;
 }
 
 /* { dg-final { scan-assembler-not "\[ \t\]add\[ql\]" } } */

diff --git a/gcc/testsuite/gcc.target/alpha/pr83628-3.c b/gcc/testsuite/gcc.target/alpha/pr83628-3.c
new file mode 100644 (file)
index 0000000..5bec89f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/alpha/pr83628-3.c
@@ -0,0 +1,29 @@
+/* PR target/83628 */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int
+s4l (int a, int b)
+{
+  return a * 4 - b;
+}
+
+int
+s8l (int a, int b)
+{
+  return a * 8 - b;
+}
+
+long
+s4q (long a, long b)
+{
+  return a * 4 - b;
+}
+
+long
+s8q (long a, long b)
+{
+  return a * 8 - b;
+}
+
+/* { dg-final { scan-assembler-not "\[ \t\]sub\[ql\]" } } */