base simple cpu: removes commented out code about cache ops

diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 4db1c6c10d520cf89f577725d25349b0b990e0d1..012a49253dc221dc736810dc9363a622ab6e222a 100644 (file)
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -521,38 +521,3 @@ BaseSimpleCPU::startup()
     BaseCPU::startup();
     thread->startup();
 }
-
-/*Fault
-BaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr)
-{
-    // translate to physical address
-    Fault fault = NoFault;
-    int CacheID = Op & 0x3; // Lower 3 bits identify Cache
-    int CacheOP = Op >> 2; // Upper 3 bits identify Cache Operation
-    if(CacheID > 1)
-      {
-        warn("CacheOps not implemented for secondary/tertiary caches\n");
-      }
-    else
-      {
-        switch(CacheOP)
-          { // Fill Packet Type
-          case 0: warn("Invalidate Cache Op\n");
-            break;
-          case 1: warn("Index Load Tag Cache Op\n");
-            break;
-          case 2: warn("Index Store Tag Cache Op\n");
-            break;
-          case 4: warn("Hit Invalidate Cache Op\n");
-            break;
-          case 5: warn("Fill/Hit Writeback Invalidate Cache Op\n");
-            break;
-          case 6: warn("Hit Writeback\n");
-            break;
-          case 7: warn("Fetch & Lock Cache Op\n");
-            break;
-          default: warn("Unimplemented Cache Op\n");
-          }
-      }
-    return fault;
-}*/