else if (ALTIVEC_REGNO_P (regno))
reg_size = UNITS_PER_ALTIVEC_WORD;
- /* The value returned for SCmode in the E500 double case is 2 for
- ABI compatibility; storing an SCmode value in a single register
- would require function_arg and rs6000_spe_function_arg to handle
- SCmode so as to pass the value correctly in a pair of
- registers. */
- else if (TARGET_E500_DOUBLE && FLOAT_MODE_P (mode) && mode != SCmode
- && !DECIMAL_FLOAT_MODE_P (mode) && SPE_SIMD_REGNO_P (regno))
- reg_size = UNITS_PER_FP_WORD;
-
else
reg_size = UNITS_PER_WORD;
fprintf (stderr, DEBUG_FMT_S, "soft_float",
(TARGET_SOFT_FLOAT ? "true" : "false"));
- fprintf (stderr, DEBUG_FMT_S, "e500_single",
- (TARGET_E500_SINGLE ? "true" : "false"));
-
- fprintf (stderr, DEBUG_FMT_S, "e500_double",
- (TARGET_E500_DOUBLE ? "true" : "false"));
-
if (TARGET_LINK_STACK)
fprintf (stderr, DEBUG_FMT_S, "link_stack", "true");
&& !complex_p
&& !small_int_vsx_p
&& (m2 != DFmode || !TARGET_UPPER_REGS_DF)
- && (m2 != SFmode || !TARGET_UPPER_REGS_SF)
- && !(TARGET_E500_DOUBLE && msize == 8))
+ && (m2 != SFmode || !TARGET_UPPER_REGS_SF))
{
addr_mask |= RELOAD_REG_PRE_INCDEC;
}
}
- if (TARGET_E500_DOUBLE)
- rs6000_class_max_nregs[DFmode][GENERAL_REGS] = 1;
-
/* Calculate which modes to automatically generate code to use a the
reciprocal divide and square root instructions. In the future, possibly
automatically generate the instructions even if the user did not specify
case PROCESSOR_PPCE5500:
case PROCESSOR_PPCE6500:
- rs6000_single_float = TARGET_E500_SINGLE || TARGET_E500_DOUBLE;
- rs6000_double_float = TARGET_E500_DOUBLE;
+ rs6000_single_float = 0;
+ rs6000_double_float = 0;
rs6000_isa_flags &= ~OPTION_MASK_STRING;
"point");
}
- /* Detect invalid option combinations with E500. */
- CHECK_E500_OPTIONS;
-
rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
&& rs6000_cpu != PROCESSOR_POWER5
&& rs6000_cpu != PROCESSOR_POWER6
bool
invalid_e500_subreg (rtx op, machine_mode mode)
{
- if (TARGET_E500_DOUBLE)
- {
- /* Reject (subreg:SI (reg:DF)); likewise with subreg:DI or
- subreg:TI and reg:TF. Decimal float modes are like integer
- modes (only low part of each register used) for this
- purpose. */
- if (GET_CODE (op) == SUBREG
- && (mode == SImode || mode == DImode || mode == TImode
- || mode == DDmode || mode == TDmode || mode == PTImode)
- && REG_P (SUBREG_REG (op))
- && (GET_MODE (SUBREG_REG (op)) == DFmode
- || GET_MODE (SUBREG_REG (op)) == TFmode
- || GET_MODE (SUBREG_REG (op)) == IFmode
- || GET_MODE (SUBREG_REG (op)) == KFmode))
- return true;
-
- /* Reject (subreg:DF (reg:DI)); likewise with subreg:TF and
- reg:TI. */
- if (GET_CODE (op) == SUBREG
- && (mode == DFmode || mode == TFmode || mode == IFmode
- || mode == KFmode)
- && REG_P (SUBREG_REG (op))
- && (GET_MODE (SUBREG_REG (op)) == DImode
- || GET_MODE (SUBREG_REG (op)) == TImode
- || GET_MODE (SUBREG_REG (op)) == PTImode
- || GET_MODE (SUBREG_REG (op)) == DDmode
- || GET_MODE (SUBREG_REG (op)) == TDmode))
- return true;
- }
-
if (TARGET_SPE
&& GET_CODE (op) == SUBREG
&& mode == SImode
else if (align < 128)
align = 128;
}
- else if (TARGET_E500_DOUBLE
- && TREE_CODE (type) == REAL_TYPE
- && TYPE_MODE (type) == DFmode)
- {
- if (align < 64)
- align = 64;
- }
}
if (how != align_abi)
case DFmode:
case DDmode:
case DImode:
- /* On e500v2, we may have:
-
- (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
-
- Which gets addressed with evldd instructions. */
- if (TARGET_E500_DOUBLE)
- return SPE_CONST_OFFSET_OK (offset);
-
/* If we are using VSX scalar loads, restrict ourselves to reg+reg
addressing. */
if (VECTOR_MEM_VSX_P (mode))
case TDmode:
case TImode:
case PTImode:
- if (TARGET_E500_DOUBLE)
- return (SPE_CONST_OFFSET_OK (offset)
- && SPE_CONST_OFFSET_OK (offset + 8));
-
extra = 8;
if (!worst_case)
break;
/* quad word addresses are restricted, and we can't use LO_SUM. */
if (mode_supports_vsx_dform_quad (mode))
return false;
- /* Restrict addressing for DI because of our SUBREG hackery. */
- if (TARGET_E500_DOUBLE && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
- return false;
x = XEXP (x, 1);
if (TARGET_ELF || TARGET_MACHO)
&& GET_CODE (XEXP (x, 1)) == CONST_INT
&& ((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000)
>= 0x10000 - extra)
- && !(SPE_VECTOR_MODE (mode)
- || (TARGET_E500_DOUBLE && GET_MODE_SIZE (mode) > UNITS_PER_WORD)))
+ && !SPE_VECTOR_MODE (mode))
{
HOST_WIDE_INT high_int, low_int;
rtx sum;
return gen_rtx_PLUS (Pmode, XEXP (x, 0),
force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
}
- else if (SPE_VECTOR_MODE (mode)
- || (TARGET_E500_DOUBLE && GET_MODE_SIZE (mode) > UNITS_PER_WORD))
+ else if (SPE_VECTOR_MODE (mode))
{
if (mode == DImode)
return x;
&& CONST_INT_P (XEXP (x, 1))
&& reg_offset_p
&& !SPE_VECTOR_MODE (mode)
- && !(TARGET_E500_DOUBLE && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
&& (quad_offset_p || !VECTOR_MODE_P (mode) || VECTOR_MEM_NONE_P (mode)))
{
HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
if (!FLOAT128_2REG_P (mode)
&& ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
|| TARGET_POWERPC64
- || (mode != DFmode && mode != DDmode)
- || (TARGET_E500_DOUBLE && mode != DDmode))
+ || (mode != DFmode && mode != DDmode))
&& (TARGET_POWERPC64 || mode != DImode)
&& (mode != TImode || VECTOR_MEM_VSX_P (TImode))
&& mode != PTImode
fit into 1, whereas DI still needs two. */
static bool
-rs6000_member_type_forces_blk (const_tree field, machine_mode mode)
+rs6000_member_type_forces_blk (const_tree field, machine_mode)
{
- return ((TARGET_SPE && TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
- || (TARGET_E500_DOUBLE && mode == DFmode));
+ return (TARGET_SPE && TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE);
}
\f
/* Nonzero if we can use a floating-point register to pass this arg. */
0);
}
-static rtx
-spe_build_register_parallel (machine_mode mode, int gregno)
-{
- rtx r1, r3, r5, r7;
-
- switch (mode)
- {
- case DFmode:
- r1 = gen_rtx_REG (DImode, gregno);
- r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
- return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1));
-
- case DCmode:
- case TFmode:
- r1 = gen_rtx_REG (DImode, gregno);
- r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
- r3 = gen_rtx_REG (DImode, gregno + 2);
- r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
- return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3));
-
- case TCmode:
- r1 = gen_rtx_REG (DImode, gregno);
- r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
- r3 = gen_rtx_REG (DImode, gregno + 2);
- r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
- r5 = gen_rtx_REG (DImode, gregno + 4);
- r5 = gen_rtx_EXPR_LIST (VOIDmode, r5, GEN_INT (16));
- r7 = gen_rtx_REG (DImode, gregno + 6);
- r7 = gen_rtx_EXPR_LIST (VOIDmode, r7, GEN_INT (24));
- return gen_rtx_PARALLEL (mode, gen_rtvec (4, r1, r3, r5, r7));
-
- default:
- gcc_unreachable ();
- }
-}
-
/* Determine where to put a SIMD argument on the SPE. */
static rtx
rs6000_spe_function_arg (const CUMULATIVE_ARGS *cum, machine_mode mode,
{
int gregno = cum->sysv_gregno;
- /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
- are passed and returned in a pair of GPRs for ABI compatibility. */
- if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
- || mode == DCmode || mode == TCmode))
- {
- int n_words = rs6000_arg_size (mode, type);
-
- /* Doubles go in an odd/even register pair (r5/r6, etc). */
- if (mode == DFmode)
- gregno += (1 - gregno) & 1;
-
- /* Multi-reg args are not split between registers and stack. */
- if (gregno + n_words - 1 > GP_ARG_MAX_REG)
- return NULL_RTX;
-
- return spe_build_register_parallel (mode, gregno);
- }
if (cum->stdarg)
{
int n_words = rs6000_arg_size (mode, type);
return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
}
}
- else if (TARGET_SPE_ABI && TARGET_SPE
- && (SPE_VECTOR_MODE (mode)
- || (TARGET_E500_DOUBLE && (mode == DFmode
- || mode == DCmode
- || mode == TFmode
- || mode == TCmode))))
+ else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode))
return rs6000_spe_function_arg (cum, mode, type);
else if (abi == ABI_V4)
return false;
}
- if (TARGET_E500_DOUBLE
- && ((((to) == DFmode) + ((from) == DFmode)) == 1
- || (((to) == TFmode) + ((from) == TFmode)) == 1
- || (((to) == IFmode) + ((from) == IFmode)) == 1
- || (((to) == KFmode) + ((from) == KFmode)) == 1
- || (((to) == DDmode) + ((from) == DDmode)) == 1
- || (((to) == TDmode) + ((from) == TDmode)) == 1
- || (((to) == DImode) + ((from) == DImode)) == 1))
- return true;
-
/* Since the VSX register set includes traditional floating point registers
and altivec registers, just check for the size being different instead of
trying to check whether the modes are vector modes. Otherwise it won't
tmp = XEXP (x, 0);
/* Ugly hack because %y is overloaded. */
- if ((TARGET_SPE || TARGET_E500_DOUBLE)
+ if (TARGET_SPE
&& (GET_MODE_SIZE (GET_MODE (x)) == 8
|| FLOAT128_2REG_P (GET_MODE (x))
|| GET_MODE (x) == TImode
((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? DFmode : SFmode);
else if (ALTIVEC_REGNO_P (reg))
reg_mode = V16QImode;
- else if (TARGET_E500_DOUBLE && FLOAT128_2REG_P (mode))
- reg_mode = DFmode;
else
reg_mode = word_mode;
reg_mode_size = GET_MODE_SIZE (reg_mode);
if (SPE_VECTOR_MODE (mode))
return true;
- if (TARGET_E500_DOUBLE
- && (mode == DFmode || FLOAT128_2REG_P (mode)))
- return true;
}
}
}
/* Some cases that need register indexed addressing. */
gcc_checking_assert (!((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
|| (TARGET_VSX && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
- || (TARGET_E500_DOUBLE && mode == DFmode)
|| (TARGET_SPE_ABI
&& SPE_VECTOR_MODE (mode)
&& !SPE_CONST_OFFSET_OK (offset))));
int_rtx = GEN_INT (offset);
- if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode) && !SPE_CONST_OFFSET_OK (offset))
- || (TARGET_E500_DOUBLE && mode == DFmode))
+ if (TARGET_SPE_ABI && SPE_VECTOR_MODE (mode) && !SPE_CONST_OFFSET_OK (offset))
{
offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
emit_move_insn (offset_rtx, int_rtx);
&& TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
&& ALTIVEC_OR_VSX_VECTOR_MODE (mode))
regno = ALTIVEC_ARG_RETURN;
- else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
- && (mode == DFmode || mode == DCmode
- || FLOAT128_IBM_P (mode) || mode == TCmode))
- return spe_build_register_parallel (mode, GP_ARG_RETURN);
else
regno = GP_ARG_RETURN;
regno = ALTIVEC_ARG_RETURN;
else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
return rs6000_complex_function_value (mode);
- else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
- && (mode == DFmode || mode == DCmode
- || FLOAT128_IBM_P (mode) || mode == TCmode))
- return spe_build_register_parallel (mode, GP_ARG_RETURN);
else
regno = GP_ARG_RETURN;
if (TARGET_SPE
&& regno < 32
- && (SPE_VECTOR_MODE (GET_MODE (reg))
- || (TARGET_E500_DOUBLE && FLOAT_MODE_P (mode)
- && mode != SFmode && mode != SDmode && mode != SCmode)))
+ && SPE_VECTOR_MODE (GET_MODE (reg)))
;
else
return NULL_RTX;
; Any hardware-supported floating-point mode
(define_mode_iterator FP [
- (SF "TARGET_HARD_FLOAT && (TARGET_SINGLE_FLOAT || TARGET_E500_SINGLE)")
- (DF "TARGET_HARD_FLOAT && (TARGET_DOUBLE_FLOAT || TARGET_E500_DOUBLE)")
+ (SF "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT")
+ (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")
(TF "TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128")
(IF "TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128")
(KF "TARGET_FLOAT128_TYPE")
(define_mode_attr f64_p9 [(DF "wb") (DD "wn")])
; These modes do not fit in integer registers in 32-bit mode.
-; but on e500v2, the gpr are 64 bit registers
-(define_mode_iterator DIFD [DI (DF "!TARGET_E500_DOUBLE") DD])
+(define_mode_iterator DIFD [DI DF DD])
; Iterator for reciprocal estimate instructions
(define_mode_iterator RECIPF [SF DF V4SF V2DF])
(define_mode_attr SI_CONVERT_FP [(SF "TARGET_FCFIDS")
(DF "TARGET_FCFID")])
-(define_mode_attr E500_CONVERT [(SF "0")
- (DF "TARGET_E500_DOUBLE")])
-
(define_mode_attr TARGET_FLOAT [(SF "TARGET_SINGLE_FLOAT")
(DF "TARGET_DOUBLE_FLOAT")])
(define_expand "extendsfdf2"
[(set (match_operand:DF 0 "gpc_reg_operand")
(float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand")))]
- "TARGET_HARD_FLOAT && (TARGET_DOUBLE_FLOAT || TARGET_E500_DOUBLE)"
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
{
if (HONOR_SNANS (SFmode))
operands[1] = force_reg (SFmode, operands[1]);
(define_expand "truncdfsf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "")
(float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
- "TARGET_HARD_FLOAT && (TARGET_DOUBLE_FLOAT || TARGET_E500_DOUBLE)"
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"")
(define_insn "*truncdfsf2_fpr"
(clobber (match_dup 4))
(clobber (match_dup 5))
(clobber (match_dup 6))])]
- "TARGET_HARD_FLOAT && (TARGET_DOUBLE_FLOAT || TARGET_E500_DOUBLE)"
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"
{
- if (TARGET_E500_DOUBLE)
- {
- if (!REG_P (operands[1]))
- operands[1] = force_reg (SImode, operands[1]);
- emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
- DONE;
- }
- else if (TARGET_LFIWAX && TARGET_FCFID)
+ if (TARGET_LFIWAX && TARGET_FCFID)
{
emit_insn (gen_floatsidf2_lfiwax (operands[0], operands[1]));
DONE;
(use (match_dup 3))
(clobber (match_dup 4))
(clobber (match_dup 5))])]
- "TARGET_HARD_FLOAT && (TARGET_DOUBLE_FLOAT || TARGET_E500_DOUBLE)"
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"
{
- if (TARGET_E500_DOUBLE)
- {
- if (!REG_P (operands[1]))
- operands[1] = force_reg (SImode, operands[1]);
- emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
- DONE;
- }
- else if (TARGET_LFIWZX && TARGET_FCFID)
+ if (TARGET_LFIWZX && TARGET_FCFID)
{
emit_insn (gen_floatunssidf2_lfiwzx (operands[0], operands[1]));
DONE;
(define_expand "fix_trunc<mode>si2"
[(set (match_operand:SI 0 "gpc_reg_operand" "")
(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
- "TARGET_HARD_FLOAT && (<TARGET_FLOAT> || <E500_CONVERT>)"
+ "TARGET_HARD_FLOAT && <TARGET_FLOAT>"
"
{
- if (!<E500_CONVERT> && !TARGET_VSX_SMALL_INTEGER)
+ if (!TARGET_VSX_SMALL_INTEGER)
{
rtx src = force_reg (<MODE>mode, operands[1]);
(define_expand "fixuns_trunc<mode>si2"
[(set (match_operand:SI 0 "gpc_reg_operand" "")
(unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
- "TARGET_HARD_FLOAT
- && ((<TARGET_FLOAT> && TARGET_FCTIWUZ && TARGET_STFIWX) || <E500_CONVERT>)"
+ "TARGET_HARD_FLOAT && <TARGET_FLOAT> && TARGET_FCTIWUZ && TARGET_STFIWX"
"
{
- if (!<E500_CONVERT> && !TARGET_VSX_SMALL_INTEGER)
+ if (!TARGET_VSX_SMALL_INTEGER)
{
emit_insn (gen_fixuns_trunc<mode>si2_stfiwx (operands[0], operands[1]));
DONE;
[(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,r,r,r")
(match_operand:FMOVE64 1 "input_operand" "r,Y,r,G,H,F"))]
"! TARGET_POWERPC64
- && (TARGET_SINGLE_FLOAT || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE
- || (<MODE>mode == DDmode && TARGET_E500_DOUBLE))
+ && (TARGET_SINGLE_FLOAT || TARGET_SOFT_FLOAT)
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
"#"
{
if (FLOAT128_IEEE_P (<MODE>mode))
rs6000_expand_float128_convert (operands[0], operands[1], false);
- else if (TARGET_E500_DOUBLE)
- {
- gcc_assert (<MODE>mode == TFmode);
- emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
- }
else if (TARGET_VSX)
{
if (<MODE>mode == TFmode)
{
if (FLOAT128_IEEE_P (<MODE>mode))
rs6000_expand_float128_convert (operands[0], operands[1], false);
- else if (TARGET_E500_DOUBLE)
- {
- gcc_assert (<MODE>mode == TFmode);
- emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
- }
else if (<MODE>mode == TFmode)
emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
else if (<MODE>mode == IFmode)
{
if (FLOAT128_IEEE_P (<MODE>mode))
rs6000_expand_float128_convert (op0, op1, false);
- else if (TARGET_E500_DOUBLE && <MODE>mode == TFmode)
- emit_insn (gen_spe_fix_trunctfsi2 (op0, op1));
else if (<MODE>mode == TFmode)
emit_insn (gen_fix_trunctfsi2_fprs (op0, op1));
else if (<MODE>mode == IFmode)
}
label = gen_label_rtx ();
- if (TARGET_E500_DOUBLE && <MODE>mode == TFmode)
- {
- if (flag_finite_math_only && !flag_trapping_math)
- emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
- else
- emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
- }
- else if (<MODE>mode == TFmode)
+ if (<MODE>mode == TFmode)
emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
else if (<MODE>mode == TFmode)
emit_insn (gen_absif2_internal (operands[0], operands[1], label));
;; clobber outputs. Although those sets expand to multi-ppc-insn
;; sequences, using get_attr_length here will smash the operands
;; array. Neither is there an early_cobbler_p predicate.
-;; Disallow subregs for E500 so we don't munge frob_di_df_2.
;; Also this optimization interferes with scalars going into
;; altivec registers (the code does reloading through the FPRs).
(define_peephole2
(match_operand:DF 1 "any_operand" ""))
(set (match_operand:DF 2 "gpc_reg_operand" "")
(match_dup 0))]
- "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
- && !TARGET_UPPER_REGS_DF
+ "!TARGET_UPPER_REGS_DF
&& peep2_reg_dead_p (2, operands[0])"
[(set (match_dup 2) (match_dup 1))])
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
-(define_constants
- [(CMPDFEQ_GPR 1006)
- (TSTDFEQ_GPR 1007)
- (CMPDFGT_GPR 1008)
- (TSTDFGT_GPR 1009)
- (CMPDFLT_GPR 1010)
- (TSTDFLT_GPR 1011)
- (CMPTFEQ_GPR 1012)
- (TSTTFEQ_GPR 1013)
- (CMPTFGT_GPR 1014)
- (TSTTFGT_GPR 1015)
- (CMPTFLT_GPR 1016)
- (TSTTFLT_GPR 1017)
- ])
-
;; Modes using a 64-bit register.
(define_mode_iterator SPE64 [DF V4HI V2SF V1DI V2SI])
;; DImode and TImode.
(define_mode_iterator DITI [DI TI])
-;; Floating point conversion instructions.
-
-(define_insn "spe_fixuns_truncdfsi2"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "r")))]
- "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
- "efdctuiz %0,%1"
- [(set_attr "type" "fp")])
-
-(define_insn "spe_extendsfdf2"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
- (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "r")))]
- "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
- "efdcfs %0,%1"
- [(set_attr "type" "fp")])
-
-(define_insn "spe_fix_truncdfsi2"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (fix:SI (match_operand:DF 1 "gpc_reg_operand" "r")))]
- "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
- "efdctsiz %0,%1"
- [(set_attr "type" "fp")])
-
-(define_insn "spe_floatunssidf2"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
- (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))]
- "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
- "efdcfui %0,%1"
- [(set_attr "type" "fp")])
-
-(define_insn "spe_floatsidf2"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
- (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))]
- "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
- "efdcfsi %0,%1"
- [(set_attr "type" "fp")])
-
;; SPE SIMD instructions
(define_insn "absv2si2"
(define_insn "*frob_<SPE64:mode>_<DITI:mode>"
[(set (match_operand:SPE64 0 "nonimmediate_operand" "=r,r")
(subreg:SPE64 (match_operand:DITI 1 "input_operand" "r,m") 0))]
- "(TARGET_E500_DOUBLE && <SPE64:MODE>mode == DFmode)
- || (TARGET_SPE && <SPE64:MODE>mode != DFmode)"
+ "TARGET_SPE && <SPE64:MODE>mode != DFmode"
{
switch (which_alternative)
{
(define_insn "*frob_<SPE64:mode>_ti_8"
[(set (match_operand:SPE64 0 "nonimmediate_operand" "=r")
(subreg:SPE64 (match_operand:TI 1 "input_operand" "r") 8))]
- "(TARGET_E500_DOUBLE && <SPE64:MODE>mode == DFmode)
- || (TARGET_SPE && <SPE64:MODE>mode != DFmode)"
+ "TARGET_SPE && <SPE64:MODE>mode != DFmode"
{
if (WORDS_BIG_ENDIAN)
return "evmergelo %0,%Y1,%Z1";
return "evmergelo %0,%Z1,%Y1";
})
-(define_insn "*frob_tf_ti"
- [(set (match_operand:TF 0 "gpc_reg_operand" "=r")
- (subreg:TF (match_operand:TI 1 "gpc_reg_operand" "r") 0))]
- "TARGET_E500_DOUBLE"
-{
- if (WORDS_BIG_ENDIAN)
- return "evmergelo %0,%1,%L1\;evmergelo %L0,%Y1,%Z1";
- else
- return "evmergelo %L0,%Z1,%Y1\;evmergelo %0,%L1,%1";
-}
- [(set_attr "length" "8")])
-
(define_insn "*frob_<mode>_di_2"
[(set (subreg:DI (match_operand:SPE64TF 0 "nonimmediate_operand" "+&r,r") 0)
(match_operand:DI 1 "input_operand" "r,m"))]
- "(TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
- || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode)"
+ "TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode"
{
switch (which_alternative)
{
}
})
-(define_insn "*frob_tf_di_8_2"
- [(set (subreg:DI (match_operand:TF 0 "nonimmediate_operand" "+&r,r") 8)
- (match_operand:DI 1 "input_operand" "r,m"))]
- "TARGET_E500_DOUBLE"
-{
- switch (which_alternative)
- {
- default:
- gcc_unreachable ();
- case 0:
- if (WORDS_BIG_ENDIAN)
- return "evmergelo %L0,%1,%L1";
- else
- return "evmergelo %L0,%L1,%1";
- case 1:
- return "evldd%X1 %L0,%y1";
- }
-})
-
(define_insn "*frob_di_<mode>"
[(set (match_operand:DI 0 "nonimmediate_operand" "=&r")
(subreg:DI (match_operand:SPE64TF 1 "input_operand" "r") 0))]
- "(TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
- || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode)"
+ "TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode"
{
if (WORDS_BIG_ENDIAN)
return "evmergehi %0,%1,%1\;mr %L0,%1";
}
[(set_attr "length" "8")])
-(define_insn "*frob_ti_tf"
- [(set (match_operand:TI 0 "nonimmediate_operand" "=&r")
- (subreg:TI (match_operand:TF 1 "input_operand" "r") 0))]
- "TARGET_E500_DOUBLE"
-{
- if (WORDS_BIG_ENDIAN)
- return "evmergehi %0,%1,%1\;mr %L0,%1\;evmergehi %Y0,%L1,%L1\;mr %Z0,%L1";
- else
- return "evmergehi %Z0,%L1,%L1\;mr %Y0,%L1\;evmergehi %L0,%1,%1\;mr %0,%1";
-}
- [(set_attr "length" "16")])
-
(define_insn "*frob_<DITI:mode>_<SPE64:mode>_2"
[(set (subreg:SPE64 (match_operand:DITI 0 "register_operand" "+&r,r") 0)
(match_operand:SPE64 1 "input_operand" "r,m"))]
- "(TARGET_E500_DOUBLE && <SPE64:MODE>mode == DFmode)
- || (TARGET_SPE && <SPE64:MODE>mode != DFmode)"
+ "TARGET_SPE && <SPE64:MODE>mode != DFmode"
"*
{
switch (which_alternative)
(define_insn "*frob_ti_<mode>_8_2"
[(set (subreg:SPE64 (match_operand:TI 0 "register_operand" "+&r,r") 8)
(match_operand:SPE64 1 "input_operand" "r,m"))]
- "(TARGET_E500_DOUBLE && <MODE>mode == DFmode)
- || (TARGET_SPE && <MODE>mode != DFmode)"
+ "TARGET_SPE && <MODE>mode != DFmode"
"*
{
switch (which_alternative)
}"
[(set_attr "length" "8,8")])
-(define_insn "*frob_ti_tf_2"
- [(set (subreg:TF (match_operand:TI 0 "gpc_reg_operand" "=&r") 0)
- (match_operand:TF 1 "input_operand" "r"))]
- "TARGET_E500_DOUBLE"
-{
- if (WORDS_BIG_ENDIAN)
- return "evmergehi %0,%1,%1\;mr %L0,%1\;evmergehi %Y0,%L1,%L1\;mr %Z0,%L1";
- else
- return "evmergehi %Z0,%L1,%L1\;mr %Y0,%L1\;evmergehi %L0,%1,%1\;mr %0,%1";
-}
- [(set_attr "length" "16")])
-
(define_insn "mov_si<mode>_e500_subreg0_be"
[(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r,&r") 0)
(match_operand:SI 1 "input_operand" "r,m"))]
"WORDS_BIG_ENDIAN
- && ((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
- || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode))"
+ && (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode)"
"@
evmergelo %0,%1,%0
evmergelohi %0,%0,%0\;lwz%U1%X1 %0,%1\;evmergelohi %0,%0,%0"
[(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r,r") 0)
(match_operand:SI 1 "input_operand" "r,m"))]
"!WORDS_BIG_ENDIAN
- && ((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
- || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode))"
+ && (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode)"
"@
mr %0,%1
lwz%U1%X1 %0,%1")
(lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
(match_operand 2 "" "")))]
"WORDS_BIG_ENDIAN
- && (((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
- || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode))
- && TARGET_ELF && !TARGET_64BIT && can_create_pseudo_p ())"
+ && TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode
+ && TARGET_ELF && !TARGET_64BIT && can_create_pseudo_p ()"
"#"
"&& 1"
[(pc)]
(lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
(match_operand 2 "" "")))]
"!WORDS_BIG_ENDIAN
- && (((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
- || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode))
- && TARGET_ELF && !TARGET_64BIT)"
+ && TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode
+ && TARGET_ELF && !TARGET_64BIT"
"addi %0,%1,%K2")
;; ??? Could use evstwwe for memory stores in some cases, depending on
[(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,m")
(subreg:SI (match_operand:SPE64TF 1 "register_operand" "+r,&r") 0))]
"WORDS_BIG_ENDIAN
- && ((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
- || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode))"
+ && TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode"
"@
evmergelohi %0,%1,%1
evmergelohi %1,%1,%1\;stw%U0%X0 %1,%0"
[(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,m")
(subreg:SI (match_operand:SPE64TF 1 "register_operand" "r,r") 0))]
"!WORDS_BIG_ENDIAN
- && ((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
- || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode))"
+ && TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode"
"@
mr %0,%1
stw%U0%X0 %1,%0")
[(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r,r") 4)
(match_operand:SI 1 "input_operand" "r,m"))]
"WORDS_BIG_ENDIAN
- && ((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
- || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode))"
+ && TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode"
"@
mr %0,%1
lwz%U1%X1 %0,%1")
[(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r,&r") 4)
(match_operand:SI 1 "input_operand" "r,m"))]
"!WORDS_BIG_ENDIAN
- && ((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
- || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode))"
+ && TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode"
"@
evmergelo %0,%1,%0
evmergelohi %0,%0,%0\;lwz%U1%X1 %0,%1\;evmergelohi %0,%0,%0"
(lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
(match_operand 2 "" "")))]
"WORDS_BIG_ENDIAN
- && ((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
- || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode))
+ && TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode
&& TARGET_ELF && !TARGET_64BIT"
"addi %0,%1,%K2")
(lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
(match_operand 2 "" "")))]
"!WORDS_BIG_ENDIAN
- && (((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
- || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode))
- && TARGET_ELF && !TARGET_64BIT && can_create_pseudo_p ())"
+ && TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode
+ && TARGET_ELF && !TARGET_64BIT && can_create_pseudo_p ()"
"#"
"&& 1"
[(pc)]
[(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,m")
(subreg:SI (match_operand:SPE64TF 1 "register_operand" "r,r") 4))]
"WORDS_BIG_ENDIAN
- && ((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
- || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode))"
+ && TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode"
"@
mr %0,%1
stw%U0%X0 %1,%0")
[(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,m")
(subreg:SI (match_operand:SPE64TF 1 "register_operand" "+r,&r") 4))]
"!WORDS_BIG_ENDIAN
- && ((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
- || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode))"
+ && TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode"
"@
evmergelohi %0,%1,%1
evmergelohi %1,%1,%1\;stw%U0%X0 %1,%0"
[(set_attr "length" "4,8")])
-(define_insn "*mov_sitf_e500_subreg8_be"
- [(set (subreg:SI (match_operand:TF 0 "register_operand" "+r,&r") 8)
- (match_operand:SI 1 "input_operand" "r,m"))]
- "WORDS_BIG_ENDIAN && TARGET_E500_DOUBLE"
- "@
- evmergelo %L0,%1,%L0
- evmergelohi %L0,%L0,%L0\;lwz%U1%X1 %L0,%1\;evmergelohi %L0,%L0,%L0"
- [(set_attr "length" "4,12")])
-
-(define_insn "*mov_sitf_e500_subreg8_le"
- [(set (subreg:SI (match_operand:TF 0 "register_operand" "+r,r") 8)
- (match_operand:SI 1 "input_operand" "r,m"))]
- "!WORDS_BIG_ENDIAN && TARGET_E500_DOUBLE"
- "@
- mr %L0,%1
- lwz%U1%X1 %L0,%1")
-
-(define_insn "*mov_sitf_e500_subreg8_2_be"
- [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,m")
- (subreg:SI (match_operand:TF 1 "register_operand" "+r,&r") 8))]
- "WORDS_BIG_ENDIAN && TARGET_E500_DOUBLE"
- "@
- evmergelohi %0,%L1,%L1
- evmergelohi %L1,%L1,%L1\;stw%U0%X0 %L1,%0"
- [(set_attr "length" "4,8")])
-
-(define_insn "*mov_sitf_e500_subreg8_2_le"
- [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,m")
- (subreg:SI (match_operand:TF 1 "register_operand" "r,r") 8))]
- "!WORDS_BIG_ENDIAN && TARGET_E500_DOUBLE"
- "@
- mr %0,%L1
- stw%U0%X0 %L1,%0")
-
-(define_insn "*mov_sitf_e500_subreg12_be"
- [(set (subreg:SI (match_operand:TF 0 "register_operand" "+r,r") 12)
- (match_operand:SI 1 "input_operand" "r,m"))]
- "WORDS_BIG_ENDIAN && TARGET_E500_DOUBLE"
- "@
- mr %L0,%1
- lwz%U1%X1 %L0,%1")
-
-(define_insn "*mov_sitf_e500_subreg12_le"
- [(set (subreg:SI (match_operand:TF 0 "register_operand" "+r,&r") 12)
- (match_operand:SI 1 "input_operand" "r,m"))]
- "!WORDS_BIG_ENDIAN && TARGET_E500_DOUBLE"
- "@
- evmergelo %L0,%1,%L0
- evmergelohi %L0,%L0,%L0\;lwz%U1%X1 %L0,%1\;evmergelohi %L0,%L0,%L0"
- [(set_attr "length" "4,12")])
-
-(define_insn "*mov_sitf_e500_subreg12_2_be"
- [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,m")
- (subreg:SI (match_operand:TF 1 "register_operand" "r,r") 12))]
- "WORDS_BIG_ENDIAN && TARGET_E500_DOUBLE"
- "@
- mr %0,%L1
- stw%U0%X0 %L1,%0")
-
-(define_insn "*mov_sitf_e500_subreg12_2_le"
- [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,m")
- (subreg:SI (match_operand:TF 1 "register_operand" "+r,&r") 12))]
- "!WORDS_BIG_ENDIAN && TARGET_E500_DOUBLE"
- "@
- evmergelohi %0,%L1,%L1
- evmergelohi %L1,%L1,%L1\;stw%U0%X0 %L1,%0"
- [(set_attr "length" "4,8")])
-
-;; FIXME: Allow r=CONST0.
-(define_insn "*movdf_e500_double"
- [(set (match_operand:DF 0 "rs6000_nonimmediate_operand" "=r,r,m")
- (match_operand:DF 1 "input_operand" "r,m,r"))]
- "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE
- && (gpc_reg_operand (operands[0], DFmode)
- || gpc_reg_operand (operands[1], DFmode))"
- "*
- {
- switch (which_alternative)
- {
- case 0:
- return \"evor %0,%1,%1\";
- case 1:
- return \"evldd%X1 %0,%y1\";
- case 2:
- return \"evstdd%X0 %1,%y0\";
- default:
- gcc_unreachable ();
- }
- }"
- [(set_attr "type" "*,vecload,vecstore")
- (set_attr "length" "*,*,*")])
-
-(define_insn "spe_truncdfsf2"
- [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
- (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "r")))]
- "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
- "efscfd %0,%1")
-
-(define_insn "spe_absdf2"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
- (abs:DF (match_operand:DF 1 "gpc_reg_operand" "r")))]
- "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
- "efdabs %0,%1")
-
-(define_insn "spe_nabsdf2"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
- (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "r"))))]
- "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
- "efdnabs %0,%1")
-
-(define_insn "spe_negdf2"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
- (neg:DF (match_operand:DF 1 "gpc_reg_operand" "r")))]
- "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
- "efdneg %0,%1")
-
-(define_insn "spe_adddf3"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
- (plus:DF (match_operand:DF 1 "gpc_reg_operand" "r")
- (match_operand:DF 2 "gpc_reg_operand" "r")))]
- "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
- "efdadd %0,%1,%2")
-
-(define_insn "spe_subdf3"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
- (minus:DF (match_operand:DF 1 "gpc_reg_operand" "r")
- (match_operand:DF 2 "gpc_reg_operand" "r")))]
- "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
- "efdsub %0,%1,%2")
-
-(define_insn "spe_muldf3"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
- (mult:DF (match_operand:DF 1 "gpc_reg_operand" "r")
- (match_operand:DF 2 "gpc_reg_operand" "r")))]
- "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
- "efdmul %0,%1,%2")
-
-(define_insn "spe_divdf3"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
- (div:DF (match_operand:DF 1 "gpc_reg_operand" "r")
- (match_operand:DF 2 "gpc_reg_operand" "r")))]
- "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
- "efddiv %0,%1,%2")
-
-;; Double-precision floating point instructions for IBM long double.
-
-(define_insn_and_split "spe_trunctfdf2_internal1"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=r,?r")
- (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,r")))]
- "!TARGET_IEEEQUAD
- && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128"
- "@
- #
- evor %0,%1,%1"
- "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
- [(const_int 0)]
-{
- emit_note (NOTE_INSN_DELETED);
- DONE;
-})
-
-(define_insn_and_split "spe_trunctfsf2"
- [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
- (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "r")))
- (clobber (match_scratch:DF 2 "=r"))]
- "!TARGET_IEEEQUAD
- && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128"
- "#"
- "&& reload_completed"
- [(set (match_dup 2)
- (float_truncate:DF (match_dup 1)))
- (set (match_dup 0)
- (float_truncate:SF (match_dup 2)))]
- "")
-
-(define_insn "spe_extenddftf2"
- [(set (match_operand:TF 0 "rs6000_nonimmediate_operand" "=r,?r,r,o")
- (float_extend:TF (match_operand:DF 1 "input_operand" "0,r,m,r")))
- (clobber (match_scratch:DF 2 "=X,X,X,&r"))]
- "!TARGET_IEEEQUAD
- && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128"
- "@
- evxor %L0,%L0,%L0
- evor %0,%1,%1\;evxor %L0,%L0,%L0
- evldd%X1 %0,%y1\;evxor %L0,%L0,%L0
- evstdd%X0 %1,%y0\;evxor %2,%2,%2\;evstdd %2,%Y0"
- [(set_attr "length" "4,8,8,12")])
-
-(define_expand "spe_fix_trunctfsi2"
- [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
- (clobber (match_dup 2))
- (clobber (match_dup 3))
- (clobber (match_dup 4))])]
- "!TARGET_IEEEQUAD
- && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128"
-{
- operands[2] = gen_reg_rtx (DFmode);
- operands[3] = gen_reg_rtx (SImode);
- operands[4] = gen_reg_rtx (SImode);
-})
-
-; Like fix_trunc_helper, add with rounding towards 0.
-(define_insn "spe_fix_trunctfsi2_internal"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (fix:SI (match_operand:TF 1 "gpc_reg_operand" "r")))
- (clobber (match_operand:DF 2 "gpc_reg_operand" "=r"))
- (clobber (match_operand:SI 3 "gpc_reg_operand" "=&r"))
- (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))]
- "!TARGET_IEEEQUAD
- && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128"
- "mfspefscr %3\;rlwinm %4,%3,0,0,29\;ori %4,%4,1\;efdadd %2,%1,%L1\;mtspefscr %3\;efdctsiz %0, %2"
- [(set_attr "length" "24")])
-
-(define_insn "spe_negtf2_internal"
- [(set (match_operand:TF 0 "gpc_reg_operand" "=r")
- (neg:TF (match_operand:TF 1 "gpc_reg_operand" "r")))]
- "!TARGET_IEEEQUAD
- && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128"
- "*
-{
- if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
- return \"efdneg %L0,%L1\;efdneg %0,%1\";
- else
- return \"efdneg %0,%1\;efdneg %L0,%L1\";
-}"
- [(set_attr "length" "8")])
-
-(define_expand "spe_abstf2_cmp"
- [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
- (match_operand:TF 1 "gpc_reg_operand" "f"))
- (set (match_dup 3) (match_dup 5))
- (set (match_dup 5) (abs:DF (match_dup 5)))
- (set (match_dup 4) (unspec:CCFP [(compare:CCFP (match_dup 3)
- (match_dup 5))] CMPDFEQ_GPR))
- (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
- (label_ref (match_operand 2 "" ""))
- (pc)))
- (set (match_dup 6) (neg:DF (match_dup 6)))]
- "!TARGET_IEEEQUAD
- && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128"
- "
-{
- const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
- const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
- operands[3] = gen_reg_rtx (DFmode);
- operands[4] = gen_reg_rtx (CCFPmode);
- operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
- operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
-}")
-
-(define_expand "spe_abstf2_tst"
- [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
- (match_operand:TF 1 "gpc_reg_operand" "f"))
- (set (match_dup 3) (match_dup 5))
- (set (match_dup 5) (abs:DF (match_dup 5)))
- (set (match_dup 4) (unspec:CCFP [(compare:CCFP (match_dup 3)
- (match_dup 5))] TSTDFEQ_GPR))
- (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
- (label_ref (match_operand 2 "" ""))
- (pc)))
- (set (match_dup 6) (neg:DF (match_dup 6)))]
- "!TARGET_IEEEQUAD
- && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128"
- "
-{
- const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
- const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
- operands[3] = gen_reg_rtx (DFmode);
- operands[4] = gen_reg_rtx (CCFPmode);
- operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
- operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
-}")
-
;; Vector move instructions.
(define_expand "movv2si"
;; We have 2 variants for each. One for IEEE compliant math and one
;; for non IEEE compliant math.
-;; Same thing, but for double-precision.
-
-(define_insn "cmpdfeq_gpr"
- [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
- (unspec:CCFP
- [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
- (match_operand:DF 2 "gpc_reg_operand" "r"))]
- CMPDFEQ_GPR))]
- "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE
- && !(flag_finite_math_only && !flag_trapping_math)"
- "efdcmpeq %0,%1,%2"
- [(set_attr "type" "veccmp")])
-
-(define_insn "tstdfeq_gpr"
- [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
- (unspec:CCFP
- [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
- (match_operand:DF 2 "gpc_reg_operand" "r"))]
- TSTDFEQ_GPR))]
- "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE
- && flag_finite_math_only && !flag_trapping_math"
- "efdtsteq %0,%1,%2"
- [(set_attr "type" "veccmpsimple")])
-
-(define_insn "cmpdfgt_gpr"
- [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
- (unspec:CCFP
- [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
- (match_operand:DF 2 "gpc_reg_operand" "r"))]
- CMPDFGT_GPR))]
- "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE
- && !(flag_finite_math_only && !flag_trapping_math)"
- "efdcmpgt %0,%1,%2"
- [(set_attr "type" "veccmp")])
-
-(define_insn "tstdfgt_gpr"
- [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
- (unspec:CCFP
- [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
- (match_operand:DF 2 "gpc_reg_operand" "r"))]
- TSTDFGT_GPR))]
- "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE
- && flag_finite_math_only && !flag_trapping_math"
- "efdtstgt %0,%1,%2"
- [(set_attr "type" "veccmpsimple")])
-
-(define_insn "cmpdflt_gpr"
- [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
- (unspec:CCFP
- [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
- (match_operand:DF 2 "gpc_reg_operand" "r"))]
- CMPDFLT_GPR))]
- "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE
- && !(flag_finite_math_only && !flag_trapping_math)"
- "efdcmplt %0,%1,%2"
- [(set_attr "type" "veccmp")])
-
-(define_insn "tstdflt_gpr"
- [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
- (unspec:CCFP
- [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
- (match_operand:DF 2 "gpc_reg_operand" "r"))]
- TSTDFLT_GPR))]
- "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE
- && flag_finite_math_only && !flag_trapping_math"
- "efdtstlt %0,%1,%2"
- [(set_attr "type" "veccmpsimple")])
-
-;; Same thing, but for IBM long double.
-
-(define_insn "cmptfeq_gpr"
- [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
- (unspec:CCFP
- [(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "r")
- (match_operand:TF 2 "gpc_reg_operand" "r"))]
- CMPTFEQ_GPR))]
- "!TARGET_IEEEQUAD
- && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128
- && !(flag_finite_math_only && !flag_trapping_math)"
- "efdcmpeq %0,%1,%2\;bng %0,$+8\;efdcmpeq %0,%L1,%L2"
- [(set_attr "type" "veccmp")
- (set_attr "length" "12")])
-
-(define_insn "tsttfeq_gpr"
- [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
- (unspec:CCFP
- [(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "r")
- (match_operand:TF 2 "gpc_reg_operand" "r"))]
- TSTTFEQ_GPR))]
- "!TARGET_IEEEQUAD
- && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128
- && flag_finite_math_only && !flag_trapping_math"
- "efdtsteq %0,%1,%2\;bng %0,$+8\;efdtsteq %0,%L1,%L2"
- [(set_attr "type" "veccmpsimple")
- (set_attr "length" "12")])
-
-(define_insn "cmptfgt_gpr"
- [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
- (unspec:CCFP
- [(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "r")
- (match_operand:TF 2 "gpc_reg_operand" "r"))]
- CMPTFGT_GPR))]
- "!TARGET_IEEEQUAD
- && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128
- && !(flag_finite_math_only && !flag_trapping_math)"
- "efdcmpgt %0,%1,%2\;bgt %0,$+16\;efdcmpeq %0,%1,%2\;bng %0,$+8\;efdcmpgt %0,%L1,%L2"
- [(set_attr "type" "veccmp")
- (set_attr "length" "20")])
-
-(define_insn "tsttfgt_gpr"
- [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
- (unspec:CCFP
- [(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "r")
- (match_operand:TF 2 "gpc_reg_operand" "r"))]
- TSTTFGT_GPR))]
- "!TARGET_IEEEQUAD
- && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128
- && flag_finite_math_only && !flag_trapping_math"
- "efdtstgt %0,%1,%2\;bgt %0,$+16\;efdtsteq %0,%1,%2\;bng %0,$+8\;efdtstgt %0,%L1,%L2"
- [(set_attr "type" "veccmpsimple")
- (set_attr "length" "20")])
-
-(define_insn "cmptflt_gpr"
- [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
- (unspec:CCFP
- [(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "r")
- (match_operand:TF 2 "gpc_reg_operand" "r"))]
- CMPTFLT_GPR))]
- "!TARGET_IEEEQUAD
- && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128
- && !(flag_finite_math_only && !flag_trapping_math)"
- "efdcmplt %0,%1,%2\;bgt %0,$+16\;efdcmpeq %0,%1,%2\;bng %0,$+8\;efdcmplt %0,%L1,%L2"
- [(set_attr "type" "veccmp")
- (set_attr "length" "20")])
-
-(define_insn "tsttflt_gpr"
- [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
- (unspec:CCFP
- [(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "r")
- (match_operand:TF 2 "gpc_reg_operand" "r"))]
- TSTTFLT_GPR))]
- "!TARGET_IEEEQUAD
- && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128
- && flag_finite_math_only && !flag_trapping_math"
- "efdtstlt %0,%1,%2\;bgt %0,$+16\;efdtsteq %0,%1,%2\;bng %0,$+8\;efdtstlt %0,%L1,%L2"
- [(set_attr "type" "veccmpsimple")
- (set_attr "length" "20")])
-
;; Out-of-line prologues and epilogues.
(define_insn "*save_gpregs_spe"
[(match_parallel 0 "any_parallel_operand"
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