clarify bitwidth

diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn
index fa8eb6b8580dd5483070ce5c6a4b2464d3ad5c21..aaf45034cf41d9bd51db948083dc9398670c7dab 100644 (file)
--- a/simple_v_extension/specification.mdwn
+++ b/simple_v_extension/specification.mdwn
@@ -1300,8 +1300,9 @@ rd bitwidths).  The pseudo-code is therefore as follows:
         if (int_vec[rs1].isvector)  { irs1 += 1; }
         if (int_vec[rs2].isvector)  { irs2 += 1; }
 
-Whilst sign-extension and zero-extension implementations are left out
-due to each operation being different, the above should be clear that;
+Whilst specific sign-extension and zero-extension pseudocode calls
+are left out, due to each operation being different, the above should
+be clear that;
 
 * the source operands are extended out to the maximum bitwidth of all
   source operands