i965: Re-combine the Gen4-5 and Gen6+ write_depth_count functions.
authorKenneth Graunke <kenneth@whitecape.org>
Thu, 12 Dec 2013 08:44:11 +0000 (00:44 -0800)
committerKenneth Graunke <kenneth@whitecape.org>
Mon, 20 Jan 2014 23:38:23 +0000 (15:38 -0800)
Now that we have a helper function that handles the PIPE_CONTROL
variations between the various platforms, these are basically the same.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
src/mesa/drivers/dri/i965/brw_context.h
src/mesa/drivers/dri/i965/brw_queryobj.c
src/mesa/drivers/dri/i965/gen6_queryobj.c

index b2324d260a5d7905d7559a48b528dcd30d0ee083..6a0cebed593d1070b4dd02adb538a64ef1bd7775 100644 (file)
@@ -1557,6 +1557,7 @@ void brw_emit_query_end(struct brw_context *brw);
 /** gen6_queryobj.c */
 void gen6_init_queryobj_functions(struct dd_function_table *functions);
 void brw_write_timestamp(struct brw_context *brw, drm_intel_bo *bo, int idx);
+void brw_write_depth_count(struct brw_context *brw, drm_intel_bo *bo, int idx);
 void brw_store_register_mem64(struct brw_context *brw,
                               drm_intel_bo *bo, uint32_t reg, int idx);
 
index dc26c0864e17a168a1269cbe9ada63d20c58a7dc..00ce5eba9b72d7897a36250615fb01232b15319b 100644 (file)
@@ -63,10 +63,12 @@ brw_write_timestamp(struct brw_context *brw, drm_intel_bo *query_bo, int idx)
 /**
  * Emit PIPE_CONTROLs to write the PS_DEPTH_COUNT register into a buffer.
  */
-static void
-write_depth_count(struct brw_context *brw, drm_intel_bo *query_bo, int idx)
+void
+brw_write_depth_count(struct brw_context *brw, drm_intel_bo *query_bo, int idx)
 {
-   assert(brw->gen < 6);
+   /* Emit Sandybridge workaround flush: */
+   if (brw->gen == 6)
+      intel_emit_post_sync_nonzero_flush(brw);
 
    brw_emit_pipe_control_write(brw,
                                PIPE_CONTROL_WRITE_DEPTH_COUNT
@@ -431,7 +433,7 @@ brw_emit_query_begin(struct brw_context *brw)
 
    ensure_bo_has_space(ctx, query);
 
-   write_depth_count(brw, query->bo, query->last_index * 2);
+   brw_write_depth_count(brw, query->bo, query->last_index * 2);
 
    brw->query.begin_emitted = true;
 }
@@ -453,7 +455,7 @@ brw_emit_query_end(struct brw_context *brw)
    if (!brw->query.begin_emitted)
       return;
 
-   write_depth_count(brw, query->bo, query->last_index * 2 + 1);
+   brw_write_depth_count(brw, query->bo, query->last_index * 2 + 1);
 
    brw->query.begin_emitted = false;
    query->last_index++;
index e76562393de4ae02639c72b4d48f52de2a604312..06ac64592507df6b2f66b5cf5a3f13e0065fac19 100644 (file)
 #include "intel_batchbuffer.h"
 #include "intel_reg.h"
 
-/**
- * Emit PIPE_CONTROLs to write the PS_DEPTH_COUNT register into a buffer.
- */
-static void
-write_depth_count(struct brw_context *brw, drm_intel_bo *query_bo, int idx)
-{
-   /* Emit Sandybridge workaround flush: */
-   if (brw->gen == 6)
-      intel_emit_post_sync_nonzero_flush(brw);
-
-   brw_emit_pipe_control_write(brw,
-                               PIPE_CONTROL_WRITE_DEPTH_COUNT
-                               | PIPE_CONTROL_DEPTH_STALL,
-                               query_bo, idx * sizeof(uint64_t), 0, 0);
-}
-
 /*
  * Write an arbitrary 64-bit register to a buffer via MI_STORE_REGISTER_MEM.
  *
@@ -252,7 +236,7 @@ gen6_begin_query(struct gl_context *ctx, struct gl_query_object *q)
    case GL_ANY_SAMPLES_PASSED:
    case GL_ANY_SAMPLES_PASSED_CONSERVATIVE:
    case GL_SAMPLES_PASSED_ARB:
-      write_depth_count(brw, query->bo, 0);
+      brw_write_depth_count(brw, query->bo, 0);
       break;
 
    case GL_PRIMITIVES_GENERATED:
@@ -291,7 +275,7 @@ gen6_end_query(struct gl_context *ctx, struct gl_query_object *q)
    case GL_ANY_SAMPLES_PASSED:
    case GL_ANY_SAMPLES_PASSED_CONSERVATIVE:
    case GL_SAMPLES_PASSED_ARB:
-      write_depth_count(brw, query->bo, 1);
+      brw_write_depth_count(brw, query->bo, 1);
       break;
 
    case GL_PRIMITIVES_GENERATED: