svga: fix texture swizzle writemasking

Commit bfe1e7737a76e3b046 changed how texture swizzles are set up.
This exposed a latent bug in the VMware driver: we were ignoring
the texture instruction's writemask when applying the 0 and 1
swizzle terms.

This wasn't caught by the Piglit texture swizzle test because it
only exercises fixed function (no write masking).

Fixes issues seen with ETQW apitrace.

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>

diff --git a/src/gallium/drivers/svga/svga_tgsi_vgpu10.c b/src/gallium/drivers/svga/svga_tgsi_vgpu10.c
index d29ac28240545fee86ab52294a0bde30aad150b2..96269cb872bfce99b46a0dd0edd73759c9eb54ce 100644 (file)
--- a/src/gallium/drivers/svga/svga_tgsi_vgpu10.c
+++ b/src/gallium/drivers/svga/svga_tgsi_vgpu10.c
@@ -5047,6 +5047,7 @@ end_tex_swizzle(struct svga_shader_emitter_v10 *emit,
                      ((swz_g == PIPE_SWIZZLE_0) << 1) |
                      ((swz_b == PIPE_SWIZZLE_0) << 2) |
                      ((swz_a == PIPE_SWIZZLE_0) << 3));
+      writemask_0 &= swz->inst_dst->Register.WriteMask;
 
       if (writemask_0) {
          struct tgsi_full_src_register zero = int_tex ?
@@ -5065,6 +5066,7 @@ end_tex_swizzle(struct svga_shader_emitter_v10 *emit,
                      ((swz_g == PIPE_SWIZZLE_1) << 1) |
                      ((swz_b == PIPE_SWIZZLE_1) << 2) |
                      ((swz_a == PIPE_SWIZZLE_1) << 3));
+      writemask_1 &= swz->inst_dst->Register.WriteMask;
 
       if (writemask_1) {
          struct tgsi_full_src_register one = int_tex ?