Update README.md

diff --git a/docs/examples/indinv/README.md b/docs/examples/indinv/README.md
index 8fb56d4bac1edc754a7ecc2734fca05749507ee5..3ebc3c8b8d2967e04f17759edb7d8c61292732ce 100644 (file)
--- a/docs/examples/indinv/README.md
+++ b/docs/examples/indinv/README.md
@@ -17,9 +17,12 @@ the following technique for proving and using inductive invariants.
 Consider the following circuit (stripped-down [example.sv](example.sv)):
 
 ```SystemVerilog
-module example(input logic clk, output reg [4:0] state); 
-       initial state = 27;
+module example(clk, state); 
+       input logic clk;
+       output logic [4:0] state = 27;
+
        always_ff @(posedge clk) state <= (5'd 2 * state - 5'd 1) ^ (state & 5'd 7);
+
        always_comb assert (state != 0);
 endmodule
 ```