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Improve handling of and-with-1 and or-with-0 in opt_expr, fixes #327
author
Clifford Wolf
<clifford@clifford.at>
Thu, 14 Mar 2019 19:35:15 +0000
(20:35 +0100)
committer
Clifford Wolf
<clifford@clifford.at>
Thu, 14 Mar 2019 19:52:00 +0000
(20:52 +0100)
Signed-off-by: Clifford Wolf <clifford@clifford.at>
passes/opt/opt_expr.cc
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diff --git
a/passes/opt/opt_expr.cc
b/passes/opt/opt_expr.cc
index 26a3ca7bc00948fc151c46cc47940115cd6377a7..a05db2a4fdf86d72a1ab75f4fcb9dfc6a19987af 100644
(file)
--- a/
passes/opt/opt_expr.cc
+++ b/
passes/opt/opt_expr.cc
@@
-155,6
+155,13
@@
bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
new_b.append_bit(it.first.second);
}
+ if (cell->type.in("$and", "$or") && i == GRP_CONST_A) {
+ log(" Direct Connection: %s (%s with %s)\n", log_signal(new_b), log_id(cell->type), log_signal(new_a));
+ module->connect(new_y, new_b);
+ module->connect(new_conn);
+ continue;
+ }
+
RTLIL::Cell *c = module->addCell(NEW_ID, cell->type);
c->setPort("\\A", new_a);