state->dr_ctrl_wp[i], state->dr_ref_count_wp[i]);
}
+/* Return true if debug arch level is compatible for hw watchpoints
+ and breakpoints. */
+
+static bool
+compatible_debug_arch (unsigned int debug_arch)
+{
+ if (debug_arch == AARCH64_DEBUG_ARCH_V8)
+ return true;
+ if (debug_arch == AARCH64_DEBUG_ARCH_V8_1)
+ return true;
+ if (debug_arch == AARCH64_DEBUG_ARCH_V8_2)
+ return true;
+
+ return false;
+}
+
/* Get the hardware debug register capacity information from the
process represented by TID. */
/* Get hardware watchpoint register info. */
if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_HW_WATCH, &iov) == 0
- && (AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8
- || AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8_1
- || AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8_2))
+ && compatible_debug_arch (AARCH64_DEBUG_ARCH (dreg_state.dbg_info)))
{
aarch64_num_wp_regs = AARCH64_DEBUG_NUM_SLOTS (dreg_state.dbg_info);
if (aarch64_num_wp_regs > AARCH64_HWP_MAX_NUM)
/* Get hardware breakpoint register info. */
if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_HW_BREAK, &iov) == 0
- && (AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8
- || AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8_1
- || AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8_2))
+ && compatible_debug_arch (AARCH64_DEBUG_ARCH (dreg_state.dbg_info)))
{
aarch64_num_bp_regs = AARCH64_DEBUG_NUM_SLOTS (dreg_state.dbg_info);
if (aarch64_num_bp_regs > AARCH64_HBP_MAX_NUM)