arch-power: Rename program counter registers

The Power ISA specification lists the Program Counter (PC) and
the Next Program Counter (NPC) registers as Current Instruction
Address (CIA) and Next Instruction Address (NIA). This applies
the ISA naming convention for these two registers.

Change-Id: I8b9094ab1c809f4dfdb4d7330c17f360adf063e9
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16603
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index d2365bd5b09266c5b2f7c51bc557acace7e07e6f..060d6a34d63b4fc2fb05f9ed436e12eeab7631b1 100644 (file)
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -386,12 +386,12 @@ decode OPCODE default Unknown::unknown() {
 
         // Conditionally branch relative to PC based on CR and CTR.
         format BranchPCRelCondCtr {
-            0: bc({{ NPC = (uint32_t)(PC + disp); }});
+            0: bc({{ NIA = (uint32_t)(CIA + disp); }});
         }
 
         // Conditionally branch to fixed address based on CR and CTR.
         format BranchNonPCRelCondCtr {
-            1: bca({{ NPC = targetAddr; }});
+            1: bca({{ NIA = targetAddr; }});
         }
     }
 
@@ -399,12 +399,12 @@ decode OPCODE default Unknown::unknown() {
 
         // Unconditionally branch relative to PC.
         format BranchPCRel {
-            0: b({{ NPC = (uint32_t)(PC + disp); }});
+            0: b({{ NIA = (uint32_t)(CIA + disp); }});
         }
 
         // Unconditionally branch to fixed address.
         format BranchNonPCRel {
-            1: ba({{ NPC = targetAddr; }});
+            1: ba({{ NIA = targetAddr; }});
         }
     }
 
@@ -412,12 +412,12 @@ decode OPCODE default Unknown::unknown() {
 
         // Conditionally branch to address in LR based on CR and CTR.
         format BranchLrCondCtr {
-           16: bclr({{ NPC = LR & 0xfffffffc; }});
+           16: bclr({{ NIA = LR & 0xfffffffc; }});
         }
 
         // Conditionally branch to address in CTR based on CR.
         format BranchCtrCond {
-           528: bcctr({{ NPC = CTR & 0xfffffffc; }});
+           528: bcctr({{ NIA = CTR & 0xfffffffc; }});
         }
 
         // Condition register manipulation instructions.

diff --git a/src/arch/power/isa/formats/branch.isa b/src/arch/power/isa/formats/branch.isa
index d51ed5c259db4b71a5cbb7534c4b76dcc193e3e3..728f562b67f7ec441884b5d9f1bd30e6293f4fe1 100644 (file)
--- a/src/arch/power/isa/formats/branch.isa
+++ b/src/arch/power/isa/formats/branch.isa
@@ -48,7 +48,7 @@
 let {{
 
 # Simple code to update link register (LR).
-updateLrCode = 'LR = PC + 4;'
+updateLrCode = 'LR = CIA + 4;'
 
 }};
 
@@ -105,7 +105,7 @@ def GetCondCode(br_code):
     cond_code =  'if(condOk(CR)) {\n'
     cond_code += '    ' + br_code + '\n'
     cond_code += '} else {\n'
-    cond_code += '    NPC = NPC;\n'
+    cond_code += '    NIA = NIA;\n'
     cond_code += '}\n'
     return cond_code
 
@@ -119,7 +119,7 @@ def GetCtrCondCode(br_code):
     cond_code += 'if(ctr_ok && cond_ok) {\n'
     cond_code += '    ' + br_code + '\n'
     cond_code += '} else {\n'
-    cond_code += '    NPC = NPC;\n'
+    cond_code += '    NIA = NIA;\n'
     cond_code += '}\n'
     cond_code += 'CTR = ctr;\n'
     return cond_code

diff --git a/src/arch/power/isa/operands.isa b/src/arch/power/isa/operands.isa
index 98b91dc8af1f9cf144a1f77b0d518b80ee37e9f4..a72a0714d4a72b1a25d1dbe33ab6f6101b41c9ae 100644 (file)
--- a/src/arch/power/isa/operands.isa
+++ b/src/arch/power/isa/operands.isa
@@ -59,8 +59,8 @@ def operands {{
     'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 8),
 
     # Program counter and next
-    'PC': ('PCState', 'uw', 'pc', (None, None, 'IsControl'), 9),
-    'NPC': ('PCState', 'uw', 'npc', (None, None, 'IsControl'), 9),
+    'CIA': ('PCState', 'uw', 'pc', (None, None, 'IsControl'), 9),
+    'NIA': ('PCState', 'uw', 'npc', (None, None, 'IsControl'), 9),
 
     # Control registers
     'CR': ('IntReg', 'uw', 'INTREG_CR', 'IsInteger', 9),