Last of the instruction tests.

diff --git a/sim/testsuite/ChangeLog b/sim/testsuite/ChangeLog
index d63b1d5b3e0e454490c6ade83c57d89eb50a60c9..f628bc3b04aa9f50144d9205156b60e0bedb6306 100644 (file)
--- a/sim/testsuite/ChangeLog
+++ b/sim/testsuite/ChangeLog
@@ -1,3 +1,13 @@
+Fri Feb 20 11:00:02 1998  Nick Clifton  <nickc@cygnus.com>
+
+       * sim/m32r/addv.cgs: Test ADDV instruction.
+       * sim/m32r/addv3.cgs: Test ADDV3 instruction.
+       * sim/m32r/addx.cgs: Test ADDX instruction.
+       * sim/m32r/lock.cgs: Test LOCK instruction.
+       * sim/m32r/neg.cgs: Test NEG instruction.
+       * sim/m32r/not.cgs: Test NOT instruction.
+       * sim/m32r/unlock.cgs: Test UNLOCK instruction.
+
 Thu Feb 19 11:15:45 1998  Nick Clifton  <nickc@cygnus.com>
 
        * sim/m32r/testutils.inc (mvaddr_h_gr): new macro to load an

diff --git a/sim/testsuite/sim/m32r/unlock.cgs b/sim/testsuite/sim/m32r/unlock.cgs
new file mode 100644 (file)
index 0000000..8040c3d
--- /dev/null
+++ b/sim/testsuite/sim/m32r/unlock.cgs
@@ -0,0 +1,27 @@
+# m32r testcase for unlock $src1,@$src2
+# mach(): m32r m32rx
+
+       .include "testutils.inc"
+
+       start
+
+       .global unlock
+unlock:
+       mvaddr_h_gr r4, data_loc
+       mvi_h_gr    r5, 1
+
+       lock r5, @r4
+
+       mvi_h_gr r5, 0
+       unlock r5, @r4
+
+       test_h_gr r5, 1
+
+       mvi_h_gr r5, 0
+       unlock r5, @r4  ; This should be a nop since the processor should be unlocked.
+
+       test_h_gr r5, 0
+       pass
+
+data_loc:
+       .word 0