self.bridge = Bridge()
self.t1000 = T1000()
self.t1000.attachIO(self.iobus)
- self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
+ self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()), zero = True)
self.bridge.side_a = self.iobus.port
self.bridge.side_b = self.membus.port
self.physmem.port = self.membus.port
fatal("Could not mmap!\n");
}
+ //If requested, initialize all the memory to 0
+ if(params()->zero)
+ memset(pmemAddr, 0, params()->addrRange.size());
+
pagePtr = 0;
}
Param<string> file;
Param<Range<Addr> > range;
Param<Tick> latency;
+ Param<bool> zero;
END_DECLARE_SIM_OBJECT_PARAMS(PhysicalMemory)
INIT_PARAM_DFLT(file, "memory mapped file", ""),
INIT_PARAM(range, "Device Address Range"),
- INIT_PARAM(latency, "Memory access latency")
+ INIT_PARAM(latency, "Memory access latency"),
+ INIT_PARAM(zero, "Zero initialize memory")
END_INIT_SIM_OBJECT_PARAMS(PhysicalMemory)
p->name = getInstanceName();
p->addrRange = range;
p->latency = latency;
+ p->zero = zero;
return new PhysicalMemory(p);
}
range = Param.AddrRange(AddrRange('128MB'), "Device Address")
file = Param.String('', "memory mapped file")
latency = Param.Latency(Parent.clock, "latency of an access")
+ zero = Param.Bool(False, "zero initialize memory")
class DRAMMemory(PhysicalMemory):
type = 'DRAMMemory'