ret_bad_addr = Param.Bool(False, "Return pkt status bad address on access")
update_data = Param.Bool(False, "Update the data that is returned on writes")
warn_access = Param.String("", "String to print when device is accessed")
+ fake_mem = Param.Bool(False,
+ "Is this device acting like a memory and thus may get a cache line sized req")
class BadAddr(IsaFake):
pio_addr = 0
l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff)
- flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000)
+ flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000,
+ fake_mem=True)
dmac_fake = AmbaFake(pio_addr=0x10030000)
uart1_fake = AmbaFake(pio_addr=0x1000a000)
uart2_fake = AmbaFake(pio_addr=0x1000b000)
kmi1 = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True)
l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1")
- flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1)
+ flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1,
+ fake_mem=True)
dmac_fake = AmbaFake(pio_addr=0x10030000)
uart1_fake = AmbaFake(pio_addr=0x1000a000)
uart2_fake = AmbaFake(pio_addr=0x1000b000)
Tick
IsaFake::read(PacketPtr pkt)
{
-
+ pkt->allocate();
pkt->makeAtomicResponse();
+
if (params()->warn_access != "")
warn("Device %s accessed by read to address %#x size=%d\n",
name(), pkt->getAddr(), pkt->getSize());
pkt->set(retData8);
break;
default:
- panic("invalid access size!\n");
+ if (params()->fake_mem)
+ std::memset(pkt->getPtr<uint8_t>(), 0, pkt->getSize());
+ else
+ panic("invalid access size! Device being accessed by cache?\n");
}
}
return pioDelay;