Cleanup tests
authorEddie Hung <eddie@fpgeh.com>
Sat, 15 Feb 2020 16:29:10 +0000 (08:29 -0800)
committerEddie Hung <eddie@fpgeh.com>
Thu, 27 Feb 2020 18:17:29 +0000 (10:17 -0800)
tests/arch/xilinx/bug1480.ys [new file with mode: 0644]
tests/various/bug1480.ys [deleted file]
tests/various/pmux2shiftx.v

diff --git a/tests/arch/xilinx/bug1480.ys b/tests/arch/xilinx/bug1480.ys
new file mode 100644 (file)
index 0000000..84faea0
--- /dev/null
@@ -0,0 +1,18 @@
+read_verilog << EOF
+module top(...);
+
+input signed [17:0] A;
+input signed [17:0] B;
+output X;
+output Y;
+
+wire [35:0] P;
+assign P = A * B;
+
+assign X = P[0];
+assign Y = P[35];
+
+endmodule
+EOF
+
+synth_xilinx
diff --git a/tests/various/bug1480.ys b/tests/various/bug1480.ys
deleted file mode 100644 (file)
index 84faea0..0000000
+++ /dev/null
@@ -1,18 +0,0 @@
-read_verilog << EOF
-module top(...);
-
-input signed [17:0] A;
-input signed [17:0] B;
-output X;
-output Y;
-
-wire [35:0] P;
-assign P = A * B;
-
-assign X = P[0];
-assign Y = P[35];
-
-endmodule
-EOF
-
-synth_xilinx
index 56339408058cf253b3d0b15c41f48d4559825ade..c1994e92ca62b2c44e6acd7d10b424d1606b5bda 100644 (file)
@@ -33,7 +33,7 @@ module pmux2shiftx_test (
        end
 endmodule
 
-module issue01135(input [7:0] i, output o);
+module issue01135(input [7:0] i, output reg o);
 always @*
 case (i[6:3])
     4: o <= i[0];