(no commit message)

diff --git a/openpower/sv/sprs.mdwn b/openpower/sv/sprs.mdwn
index bafa3329b71479ff64c9735a4740de19c50c418e..867169894690dd81dc2422768e400f5d1a1815d9 100644 (file)
--- a/openpower/sv/sprs.mdwn
+++ b/openpower/sv/sprs.mdwn
@@ -167,15 +167,28 @@ given the option to run through all elements in an instruction.
 This is exactly what Horizontal-First is: a for-loop from 0 to VL-1
 except that the hardware may *choose* the number of elements.
 
-*Note to programmers: changing VL during the middle of such modes
-should be done only with due care and respect for the fact that SVSTATE
-has exactly the same peer-level status as a Program Counter.*
+Elements are considered to be in the same source batch if they have
+the same `FLOOR(srcstep/hphint)`. Likewise in the same destination batch.
+Three key observations here:
+
+1. predication is **not** involved here.  the number of actual elements
+involved is considered *before* predicate masks are applied.
+2. twin predication can result in srcstep and dststep being in different
+batches
+3. batch evaluation is done *before* REMAP, making Hazard elimination easier
+   for Multi-Issue systems.
 
 *Hardare architectural note: each element within the same group may be treated as
 100% independent from any other element within that group, and therefore
 neither Register Hazards nor Memory Hazards inter-element exist.  This makes
 implementation far easier on resources.*
 
+`hphint` may legitimately be set greater than `MAXVL`. This indicates to Multi-Issue
+hardware that even though MAXVL is relatively small the batches are *still independent*
+and therefore if Multi-Issue hardware chooses to allocate several batches up to
+`MAXVL` in size they are still independent.  This helps greatly simplify Multi-Issue
+systems by significantly reducing Hazards.
+
 ## SVLR
 
 SV Link Register, exactly analogous to LR (Link Register) may