irq: Simplify xics->core irq input

Use a simple wire. common.vhdl types are better kept for things
local to the core. We can add more wires later if we need to for
HV irqs etc...

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

diff --git a/common.vhdl b/common.vhdl
index 3b1c8bc875ea89bab4b89e177f4fe41c2a2357b0..a6b3f951051174be36fe7b3ee04aa7ba7da4fda4 100644 (file)
--- a/common.vhdl
+++ b/common.vhdl
@@ -399,10 +399,6 @@ package common is
                                                               write_cr_mask => (others => '0'),
                                                               write_cr_data => (others => '0'));
 
-    type XicsToExecute1Type is record
-       irq : std_ulogic;
-    end record;
-
 end common;
 
 package body common is

diff --git a/core.vhdl b/core.vhdl
index 8ac724cb7af0dbc1d4e5da4f8ad858af34f0eda7..d02609b51d8f4476174e1d8d9cf2bb800c3a2582 100644 (file)
--- a/core.vhdl
+++ b/core.vhdl
@@ -34,7 +34,7 @@ entity core is
        dmi_wr          : in std_ulogic;
        dmi_ack         : out std_ulogic;
 
-       xics_in         : in XicsToExecute1Type;
+       ext_irq         : in std_ulogic;
 
        terminated_out   : out std_logic
         );
@@ -291,8 +291,8 @@ begin
             flush_out => flush,
            stall_out => ex1_stall_out,
             e_in => decode2_to_execute1,
-            i_in => xics_in,
             l_in => loadstore1_to_execute1,
+            ext_irq_in => ext_irq,
             l_out => execute1_to_loadstore1,
             f_out => execute1_to_fetch1,
             e_out => execute1_to_writeback,

diff --git a/execute1.vhdl b/execute1.vhdl
index feb8581f8b4a845eaad02aa5e29d72f687ae2ed2..cac8e8a93db409f59a1f058e6c86b7d9a04b206b 100644 (file)
--- a/execute1.vhdl
+++ b/execute1.vhdl
@@ -25,7 +25,7 @@ entity execute1 is
        e_in  : in Decode2ToExecute1Type;
         l_in  : in Loadstore1ToExecute1Type;
 
-       i_in : in XicsToExecute1Type;
+       ext_irq_in : std_ulogic;
 
        -- asynchronous
         l_out : out Execute1ToLoadstore1Type;
@@ -419,7 +419,7 @@ begin
                ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#900#, 64));
                report "IRQ valid: DEC";
                irq_valid := '1';
-           elsif i_in.irq = '1' then
+           elsif ext_irq_in = '1' then
                ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#500#, 64));
                report "IRQ valid: External";
                irq_valid := '1';

diff --git a/soc.vhdl b/soc.vhdl
index a9f46fd3802d31db9daecf72d698db2040ab5ad4..7aef68ac56a3a7702f753ccd8e38175a9126399a 100644 (file)
--- a/soc.vhdl
+++ b/soc.vhdl
@@ -100,7 +100,7 @@ architecture behaviour of soc is
     signal wb_xics0_out  : wb_io_slave_out;
     signal int_level_in  : std_ulogic_vector(15 downto 0);
 
-    signal xics_to_execute1 : XicsToExecute1Type;
+    signal core_ext_irq  : std_ulogic;
 
     -- Main memory signals:
     signal wb_bram_in     : wishbone_master_out;
@@ -170,7 +170,7 @@ begin
            dmi_wr => dmi_wr,
            dmi_ack => dmi_core_ack,
            dmi_req => dmi_core_req,
-           xics_in => xics_to_execute1
+           ext_irq => core_ext_irq
            );
 
     -- Wishbone bus master arbiter & mux
@@ -512,7 +512,7 @@ begin
            wb_in => wb_xics0_in,
            wb_out => wb_xics0_out,
            int_level_in => int_level_in,
-           e_out => xics_to_execute1
+           core_irq_out => core_ext_irq
            );
 
     -- BRAM Memory slave

diff --git a/xics.vhdl b/xics.vhdl
index 7d494338cfc93e94caa5f9006b38f9a02364f061..eb41c326d75d26ed6b0a98862b9719bc6c4bd509 100644 (file)
--- a/xics.vhdl
+++ b/xics.vhdl
@@ -35,7 +35,7 @@ entity xics is
 
        int_level_in : in std_ulogic_vector(LEVEL_NUM - 1 downto 0);
 
-       e_out : out XicsToExecute1Type
+       core_irq_out : out std_ulogic
         );
 end xics;
 
@@ -80,7 +80,7 @@ begin
     wb_out.dat <= r.wb_rd_data;
     wb_out.ack <= r.wb_ack;
     wb_out.stall <= '0'; -- never stall wishbone
-    e_out.irq <= r.irq;
+    core_irq_out <= r.irq;
 
     comb : process(all)
        variable v : reg_internal_t;