if (WIDTH == 4) begin
LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
.I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));
+ end else
+ if (WIDTH == 5) begin
+ wire f0, f1;
+ \$lut #(.LUT(LUT[15: 0]), .WIDTH(4)) lut0 (.A(A[1:4]), .Y(f0));
+ \$lut #(.LUT(LUT[31:16]), .WIDTH(4)) lut1 (.A(A[1:4]), .Y(f1));
+ MUX2_LUT5 mux5(.I0(f0), .I1(f1), .S0(A[0]), .O(Y));
+ end else
+ if (WIDTH == 6) begin
+ wire f0, f1;
+ \$lut #(.LUT(LUT[31: 0]), .WIDTH(5)) lut0 (.A(A[1:5]), .Y(f0));
+ \$lut #(.LUT(LUT[63:32]), .WIDTH(5)) lut1 (.A(A[1:5]), .Y(f1));
+ MUX2_LUT6 mux6(.I0(f0), .I1(f1), .S0(A[0]), .O(Y));
+ end else
+ if (WIDTH == 7) begin
+ wire f0, f1;
+ \$lut #(.LUT(LUT[63: 0]), .WIDTH(6)) lut0 (.A(A[1:6]), .Y(f0));
+ \$lut #(.LUT(LUT[127:64]), .WIDTH(6)) lut1 (.A(A[1:6]), .Y(f1));
+ MUX2_LUT7 mux7(.I0(f0), .I1(f1), .S0(A[0]), .O(Y));
+ end else
+ if (WIDTH == 8) begin
+ wire f0, f1;
+ \$lut #(.LUT(LUT[127: 0]), .WIDTH(7)) lut0 (.A(A[1:7]), .Y(f0));
+ \$lut #(.LUT(LUT[255:128]), .WIDTH(7)) lut1 (.A(A[1:7]), .Y(f1));
+ MUX2_LUT8 mux8(.I0(f0), .I1(f1), .S0(A[0]), .O(Y));
end else begin
wire _TECHMAP_FAIL_ = 1;
end
assign F = I0 ? s1[1] : s1[0];
endmodule
+module MUX2 (O, I0, I1, S0);
+ input I0,I1;
+ input S0;
+ output O;
+ assign O = S0 ? I1 : I0;
+endmodule
+
+module MUX2_LUT5 (O, I0, I1, S0);
+ input I0,I1;
+ input S0;
+ output O;
+ MUX2 mux2_lut5 (O, I0, I1, S0);
+endmodule
+
+module MUX2_LUT6 (O, I0, I1, S0);
+ input I0,I1;
+ input S0;
+ output O;
+ MUX2 mux2_lut6 (O, I0, I1, S0);
+endmodule
+
+module MUX2_LUT7 (O, I0, I1, S0);
+ input I0,I1;
+ input S0;
+ output O;
+ MUX2 mux2_lut7 (O, I0, I1, S0);
+endmodule
+
+module MUX2_LUT8 (O, I0, I1, S0);
+ input I0,I1;
+ input S0;
+ output O;
+ MUX2 mux2_lut8 (O, I0, I1, S0);
+endmodule
+
module DFF (output reg Q, input CLK, D);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
/*
- * yosys -- Yosys Open SYnthesis Suite
+ * yosys -- Yosys Open SYnthesis Suite
*
- * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
*
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
void help() YS_OVERRIDE
{
- // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
- log(" synth_gowin [options]\n");
+ log(" synth_gowin [options]\n");
log("\n");
log("This command runs synthesis for Gowin FPGAs. This work is experimental.\n");
log("\n");
- log(" -top <module>\n");
- log(" use the specified module as top module (default='top')\n");
+ log(" -top <module>\n");
+ log(" use the specified module as top module (default='top')\n");
log("\n");
- log(" -vout <file>\n");
- log(" write the design to the specified Verilog netlist file. writing of an\n");
- log(" output file is omitted if this parameter is not specified.\n");
+ log(" -vout <file>\n");
+ log(" write the design to the specified Verilog netlist file. writing of an\n");
+ log(" output file is omitted if this parameter is not specified.\n");
log("\n");
- log(" -run <from_label>:<to_label>\n");
- log(" only run the commands between the labels (see below). an empty\n");
- log(" from label is synonymous to 'begin', and empty to label is\n");
- log(" synonymous to the end of the command list.\n");
+ log(" -run <from_label>:<to_label>\n");
+ log(" only run the commands between the labels (see below). an empty\n");
+ log(" from label is synonymous to 'begin', and empty to label is\n");
+ log(" synonymous to the end of the command list.\n");
log("\n");
- log(" -nodffe\n");
- log(" do not use flipflops with CE in output netlist\n");
+ log(" -nodffe\n");
+ log(" do not use flipflops with CE in output netlist\n");
log("\n");
- log(" -nobram\n");
- log(" do not use BRAM cells in output netlist\n");
+ log(" -nobram\n");
+ log(" do not use BRAM cells in output netlist\n");
log("\n");
- log(" -nodram\n");
- log(" do not use distributed RAM cells in output netlist\n");
+ log(" -nodram\n");
+ log(" do not use distributed RAM cells in output netlist\n");
log("\n");
- log(" -noflatten\n");
- log(" do not flatten design before synthesis\n");
+ log(" -noflatten\n");
+ log(" do not flatten design before synthesis\n");
log("\n");
- log(" -retime\n");
- log(" run 'abc' with -dff option\n");
+ log(" -retime\n");
+ log(" run 'abc' with -dff option\n");
+ log("\n");
+ log(" -nowidelut\n");
+ log(" do not use muxes to implement LUTs larger than LUT4s\n");
+ log("\n");
+ log(" -abc9\n");
+ log(" use new ABC9 flow (EXPERIMENTAL)\n");
log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
}
string top_opt, vout_file;
- bool retime, nobram, nodram, flatten, nodffe;
+ bool retime, nobram, nodram, flatten, nodffe, nowidelut, abc9;
void clear_flags() YS_OVERRIDE
{
nobram = false;
nodffe = false;
nodram = false;
+ nowidelut = false;
+ abc9 = false;
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
flatten = false;
continue;
}
+ if (args[argidx] == "-nowidelut") {
+ nowidelut = true;
+ continue;
+ }
+ if (args[argidx] == "-abc9") {
+ abc9 = true;
+ continue;
+ }
break;
}
extra_args(args, argidx, design);
run("synth -run coarse");
}
- if (!nobram && check_label("bram", "(skip if -nobram)"))
+ if (!nobram && check_label("bram", "(skip if -nobram)"))
{
run("memory_bram -rules +/gowin/bram.txt");
run("techmap -map +/gowin/brams_map.v -map +/gowin/cells_sim.v");
if (check_label("map_luts"))
{
- run("abc -lut 4");
+ if (nowidelut && abc9) {
+ run("abc9 -lut 4");
+ } else if (nowidelut && !abc9) {
+ run("abc -lut 4");
+ } else if (!nowidelut && abc9) {
+ run("abc9 -lut 4:8");
+ } else if (!nowidelut && !abc9) {
+ run("abc -lut 4:8");
+ }
run("clean");
}
projects / yosys.git / commitdiff