This patch adds a port for the Linux kernel eBPF to the GNU assembler.
A testsuite and documentation updates are included.
gas/ChangeLog:
2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
* configure.ac: Handle bpf-*-* targets.
* configure.tgt (generic_target): Likewise.
* configure: Regenerate.
* Makefile.am (TARGET_CPU_CFILES): Add tc-bpf.c.
(TARGET_CPU_HFILES): Add tc-bpf.h.
* Makefile.in: Regenerated.
* config/tc-bpf.c: New file.
* config/tc-bpf.h: Likewise.
* doc/Makefile.am (CPU_DOCS): Add c-bpf.texi.
* doc/Makefile.in: Regenerated.
* doc/all.texi: set BPF.
* doc/as.texi: Add eBPF contents.
* doc/c-bpf.texi: New file.
* testsuite/gas/bpf/alu.d: New file.
* testsuite/gas/bpf/mem-be.d: Likewise.
* testsuite/gas/bpf/mem.s: Likewise.
* testsuite/gas/bpf/mem.d: Likewise.
* testsuite/gas/bpf/lddw-be.d: Likewise.
* testsuite/gas/bpf/lddw.s: Likewise.
* testsuite/gas/bpf/lddw.d: Likewise.
* testsuite/gas/bpf/jump-be.d: Likewise.
* testsuite/gas/bpf/jump.s: Likewise.
* testsuite/gas/bpf/jump.d: Likewise.
* testsuite/gas/bpf/exit-be.d: Likewise.
* testsuite/gas/bpf/exit.s: Likewise.
* testsuite/gas/bpf/exit.d: Likewise.
* testsuite/gas/bpf/call-be.d: Likewise.
* testsuite/gas/bpf/call.s: Likewise.
* testsuite/gas/bpf/call.d: Likewise.
* testsuite/gas/bpf/bpf.exp: Likewise.
* testsuite/gas/bpf/atomic-be.d: Likewise.
* testsuite/gas/bpf/atomic.s: Likewise.
* testsuite/gas/bpf/atomic.d: Likewise.
* testsuite/gas/bpf/alu-be.d: Likewise.
* testsuite/gas/bpf/alu32-be.d: Likewise.
* testsuite/gas/bpf/alu32.s: Likewise.
* testsuite/gas/bpf/alu32.d: Likewise.
* testsuite/gas/bpf/alu.s: Likewise.
* testsuite/gas/all/gas.exp: Introduce a nop_type for eBPF.
* testsuite/gas/all/org-1.s: Support nop_type 6.
* testsuite/gas/all/org-1.l: Updated to reflect changes in
org-1.s.
+2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * configure.ac: Handle bpf-*-* targets.
+ * configure.tgt (generic_target): Likewise.
+ * configure: Regenerate.
+ * Makefile.am (TARGET_CPU_CFILES): Add tc-bpf.c.
+ (TARGET_CPU_HFILES): Add tc-bpf.h.
+ * Makefile.in: Regenerated.
+ * config/tc-bpf.c: New file.
+ * config/tc-bpf.h: Likewise.
+ * doc/Makefile.am (CPU_DOCS): Add c-bpf.texi.
+ * doc/Makefile.in: Regenerated.
+ * doc/all.texi: set BPF.
+ * doc/as.texi: Add eBPF contents.
+ * doc/c-bpf.texi: New file.
+ * testsuite/gas/bpf/alu.d: New file.
+ * testsuite/gas/bpf/mem-be.d: Likewise.
+ * testsuite/gas/bpf/mem.s: Likewise.
+ * testsuite/gas/bpf/mem.d: Likewise.
+ * testsuite/gas/bpf/lddw-be.d: Likewise.
+ * testsuite/gas/bpf/lddw.s: Likewise.
+ * testsuite/gas/bpf/lddw.d: Likewise.
+ * testsuite/gas/bpf/jump-be.d: Likewise.
+ * testsuite/gas/bpf/jump.s: Likewise.
+ * testsuite/gas/bpf/jump.d: Likewise.
+ * testsuite/gas/bpf/exit-be.d: Likewise.
+ * testsuite/gas/bpf/exit.s: Likewise.
+ * testsuite/gas/bpf/exit.d: Likewise.
+ * testsuite/gas/bpf/call-be.d: Likewise.
+ * testsuite/gas/bpf/call.s: Likewise.
+ * testsuite/gas/bpf/call.d: Likewise.
+ * testsuite/gas/bpf/bpf.exp: Likewise.
+ * testsuite/gas/bpf/atomic-be.d: Likewise.
+ * testsuite/gas/bpf/atomic.s: Likewise.
+ * testsuite/gas/bpf/atomic.d: Likewise.
+ * testsuite/gas/bpf/alu-be.d: Likewise.
+ * testsuite/gas/bpf/alu32-be.d: Likewise.
+ * testsuite/gas/bpf/alu32.s: Likewise.
+ * testsuite/gas/bpf/alu32.d: Likewise.
+ * testsuite/gas/bpf/alu.s: Likewise.
+ * testsuite/gas/all/gas.exp: Introduce a nop_type for eBPF.
+ * testsuite/gas/all/org-1.s: Support nop_type 6.
+ * testsuite/gas/all/org-1.l: Updated to reflect changes in
+ org-1.s.
+
2019-05-22 John Darrington <john@darrington.wattle.id.au>
* config/tc-s12z.c (s12z_strtol): New function. (md_show_usage): Update.
config/tc-arm.c \
config/tc-avr.c \
config/tc-bfin.c \
+ config/tc-bpf.c \
config/tc-cr16.c \
config/tc-cris.c \
config/tc-crx.c \
config/tc-arm.h \
config/tc-avr.h \
config/tc-bfin.h \
+ config/tc-bpf.h \
config/tc-cr16.h \
config/tc-cris.h \
config/tc-crx.h \
prefix = @prefix@
program_transform_name = @program_transform_name@
psdir = @psdir@
+runstatedir = @runstatedir@
sbindir = @sbindir@
sharedstatedir = @sharedstatedir@
srcdir = @srcdir@
config/tc-arm.c \
config/tc-avr.c \
config/tc-bfin.c \
+ config/tc-bpf.c \
config/tc-cr16.c \
config/tc-cris.c \
config/tc-crx.c \
config/tc-arm.h \
config/tc-avr.h \
config/tc-bfin.h \
+ config/tc-bpf.h \
config/tc-cr16.h \
config/tc-cris.h \
config/tc-crx.h \
config/$(DEPDIR)/$(am__dirstamp)
config/tc-bfin.$(OBJEXT): config/$(am__dirstamp) \
config/$(DEPDIR)/$(am__dirstamp)
+config/tc-bpf.$(OBJEXT): config/$(am__dirstamp) \
+ config/$(DEPDIR)/$(am__dirstamp)
config/tc-cr16.$(OBJEXT): config/$(am__dirstamp) \
config/$(DEPDIR)/$(am__dirstamp)
config/tc-cris.$(OBJEXT): config/$(am__dirstamp) \
@AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-arm.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-avr.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-bfin.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-bpf.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-cr16.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-cris.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-crx.Po@am__quote@
--- /dev/null
+/* tc-bpf.c -- Assembler for the Linux eBPF.
+ Copyright (C) 2019 Free Software Foundation, Inc.
+ Contributed by Oracle, Inc.
+
+ This file is part of GAS, the GNU Assembler.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GAS; see the file COPYING. If not, write to
+ the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+ Boston, MA 02110-1301, USA. */
+
+#include "as.h"
+#include "subsegs.h"
+#include "symcat.h"
+#include "opcodes/bpf-desc.h"
+#include "opcodes/bpf-opc.h"
+#include "cgen.h"
+#include "elf/common.h"
+#include "elf/bpf.h"
+#include "dwarf2dbg.h"
+
+const char comment_chars[] = ";";
+const char line_comment_chars[] = "#";
+const char line_separator_chars[] = "`";
+const char EXP_CHARS[] = "eE";
+const char FLT_CHARS[] = "fFdD";
+
+/* The target specific pseudo-ops which we support. */
+const pseudo_typeS md_pseudo_table[] =
+{
+ { NULL, NULL, 0 }
+};
+
+/* ISA handling. */
+static CGEN_BITSET *bpf_isa;
+
+\f
+
+/* Command-line options processing. */
+
+enum options
+{
+ OPTION_LITTLE_ENDIAN = OPTION_MD_BASE,
+ OPTION_BIG_ENDIAN
+};
+
+struct option md_longopts[] =
+{
+ { "EL", no_argument, NULL, OPTION_LITTLE_ENDIAN },
+ { "EB", no_argument, NULL, OPTION_BIG_ENDIAN },
+ { NULL, no_argument, NULL, 0 },
+};
+
+size_t md_longopts_size = sizeof (md_longopts);
+
+const char * md_shortopts = "";
+
+extern int target_big_endian;
+
+/* Whether target_big_endian has been set while parsing command-line
+ arguments. */
+static int set_target_endian = 0;
+
+int
+md_parse_option (int c, const char * arg ATTRIBUTE_UNUSED)
+{
+ switch (c)
+ {
+ case OPTION_BIG_ENDIAN:
+ set_target_endian = 1;
+ target_big_endian = 1;
+ break;
+ case OPTION_LITTLE_ENDIAN:
+ set_target_endian = 1;
+ target_big_endian = 0;
+ break;
+ default:
+ return 0;
+ }
+
+ return 1;
+}
+
+void
+md_show_usage (FILE * stream)
+{
+ fprintf (stream, _("\nBPF options:\n"));
+ fprintf (stream, _("\
+ --EL generate code for a little endian machine\n\
+ --EB generate code for a big endian machine\n"));
+}
+
+\f
+void
+md_begin (void)
+{
+ /* Initialize the `cgen' interface. */
+
+ /* If not specified in the command line, use the host
+ endianness. */
+ if (!set_target_endian)
+ {
+#ifdef WORDS_BIGENDIAN
+ target_big_endian = 1;
+#else
+ target_big_endian = 0;
+#endif
+ }
+
+ /* Set the ISA, which depends on the target endianness. */
+ bpf_isa = cgen_bitset_create (ISA_MAX);
+ if (target_big_endian)
+ cgen_bitset_set (bpf_isa, ISA_EBPFBE);
+ else
+ cgen_bitset_set (bpf_isa, ISA_EBPFLE);
+
+ /* Set the machine number and endian. */
+ gas_cgen_cpu_desc = bpf_cgen_cpu_open (CGEN_CPU_OPEN_ENDIAN,
+ target_big_endian ?
+ CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE,
+ CGEN_CPU_OPEN_ISAS,
+ bpf_isa,
+ CGEN_CPU_OPEN_END);
+ bpf_cgen_init_asm (gas_cgen_cpu_desc);
+
+ /* This is a callback from cgen to gas to parse operands. */
+ cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand);
+
+ /* Set the machine type. */
+ bfd_default_set_arch_mach (stdoutput, bfd_arch_bpf, bfd_mach_bpf);
+}
+
+valueT
+md_section_align (segT segment, valueT size)
+{
+ int align = bfd_get_section_alignment (stdoutput, segment);
+
+ return ((size + (1 << align) - 1) & -(1 << align));
+}
+
+\f
+/* Functions concerning relocs. */
+
+/* The location from which a PC relative jump should be calculated,
+ given a PC relative reloc. */
+
+long
+md_pcrel_from_section (fixS *fixP, segT sec)
+{
+ if (fixP->fx_addsy != (symbolS *) NULL
+ && (! S_IS_DEFINED (fixP->fx_addsy)
+ || (S_GET_SEGMENT (fixP->fx_addsy) != sec)
+ || S_IS_EXTERNAL (fixP->fx_addsy)
+ || S_IS_WEAK (fixP->fx_addsy)))
+ {
+ /* The symbol is undefined (or is defined but not in this section).
+ Let the linker figure it out. */
+ return 0;
+ }
+
+ return fixP->fx_where + fixP->fx_frag->fr_address;
+}
+
+/* Write a value out to the object file, using the appropriate endianness. */
+
+void
+md_number_to_chars (char * buf, valueT val, int n)
+{
+ if (target_big_endian)
+ number_to_chars_bigendian (buf, val, n);
+ else
+ number_to_chars_littleendian (buf, val, n);
+}
+
+arelent *
+tc_gen_reloc (asection *sec, fixS *fix)
+{
+ return gas_cgen_tc_gen_reloc (sec, fix);
+}
+
+/* Return the bfd reloc type for OPERAND of INSN at fixup FIXP. This
+ is called when the operand is an expression that couldn't be fully
+ resolved. Returns BFD_RELOC_NONE if no reloc type can be found.
+ *FIXP may be modified if desired. */
+
+bfd_reloc_code_real_type
+md_cgen_lookup_reloc (const CGEN_INSN *insn ATTRIBUTE_UNUSED,
+ const CGEN_OPERAND *operand,
+ fixS *fixP)
+{
+ switch (operand->type)
+ {
+ case BPF_OPERAND_OFFSET16:
+ return BFD_RELOC_BPF_16;
+ case BPF_OPERAND_IMM32:
+ return BFD_RELOC_BPF_32;
+ case BPF_OPERAND_IMM64:
+ return BFD_RELOC_BPF_64;
+ case BPF_OPERAND_DISP16:
+ fixP->fx_pcrel = 1;
+ return BFD_RELOC_BPF_DISP16;
+ case BPF_OPERAND_DISP32:
+ fixP->fx_pcrel = 1;
+ return BFD_RELOC_BPF_DISP32;
+ default:
+ break;
+ }
+ return BFD_RELOC_NONE;
+}
+\f
+/* *FRAGP has been relaxed to its final size, and now needs to have
+ the bytes inside it modified to conform to the new size.
+
+ Called after relaxation is finished.
+ fragP->fr_type == rs_machine_dependent.
+ fragP->fr_subtype is the subtype of what the address relaxed to. */
+
+void
+md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
+ segT sec ATTRIBUTE_UNUSED,
+ fragS *fragP ATTRIBUTE_UNUSED)
+{
+ as_fatal (_("convert_frag called"));
+}
+
+int
+md_estimate_size_before_relax (fragS *fragP ATTRIBUTE_UNUSED,
+ segT segment ATTRIBUTE_UNUSED)
+{
+ as_fatal (_("estimate_size_before_relax called"));
+ return 0;
+}
+
+\f
+void
+md_apply_fix (fixS *fixP, valueT *valP, segT seg)
+{
+ /* Some fixups for instructions require special attention. This is
+ handled in the code block below. */
+ if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED)
+ {
+ int opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED;
+ const CGEN_OPERAND *operand = cgen_operand_lookup_by_num (gas_cgen_cpu_desc,
+ opindex);
+ char *where;
+
+ switch (operand->type)
+ {
+ case BPF_OPERAND_DISP32:
+ /* eBPF supports two kind of CALL instructions: the so
+ called pseudo calls ("bpf to bpf") and external calls
+ ("bpf to kernel").
+
+ Both kind of calls use the same instruction (CALL).
+ However, external calls are constructed by passing a
+ constant argument to the instruction, whereas pseudo
+ calls result from expressions involving symbols. In
+ practice, instructions requiring a fixup are interpreted
+ as pseudo-calls. If we are executing this code, this is
+ a pseudo call.
+
+ The kernel expects for pseudo-calls to be annotated by
+ having BPF_PSEUDO_CALL in the SRC field of the
+ instruction. But beware the infamous nibble-swapping of
+ eBPF and take endianness into account here.
+
+ Note that the CALL instruction has only one operand, so
+ this code is executed only once per instruction. */
+ where = fixP->fx_frag->fr_literal + fixP->fx_where;
+ cgen_put_insn_value (gas_cgen_cpu_desc, (unsigned char *) where + 1, 8,
+ target_big_endian ? 0x01 : 0x10);
+ /* Fallthrough. */
+ case BPF_OPERAND_DISP16:
+ /* The PC-relative displacement fields in jump instructions
+ shouldn't be in bytes. Instead, they hold the number of
+ 64-bit words to the target, _minus one_. */
+ *valP = (((long) (*valP)) - 8) / 8;
+ break;
+ default:
+ break;
+ }
+ }
+
+ /* And now invoke CGEN's handler, which will eventually install
+ *valP into the corresponding operand. */
+ gas_cgen_md_apply_fix (fixP, valP, seg);
+}
+
+void
+md_assemble (char *str)
+{
+ const CGEN_INSN *insn;
+ char *errmsg;
+ CGEN_FIELDS fields;
+
+#if CGEN_INT_INSN_P
+ CGEN_INSN_INT buffer[CGEN_MAX_INSN_SIZE / sizeof (CGEN_INT_INSN_P)];
+#else
+ unsigned char buffer[CGEN_MAX_INSN_SIZE];
+ memset (buffer, 0, CGEN_MAX_INSN_SIZE); /* XXX to remove when CGEN
+ is fixed to handle
+ opcodes-in-words
+ properly. */
+#endif
+
+ gas_cgen_init_parse ();
+ insn = bpf_cgen_assemble_insn (gas_cgen_cpu_desc, str, &fields,
+ buffer, &errmsg);
+
+ if (insn == NULL)
+ {
+ as_bad ("%s", errmsg);
+ return;
+ }
+
+ gas_cgen_finish_insn (insn, buffer, CGEN_FIELDS_BITSIZE (&fields),
+ 0, /* zero to ban relaxable insns. */
+ NULL); /* NULL so results not returned here. */
+}
+
+void
+md_operand (expressionS *expressionP)
+{
+ gas_cgen_md_operand (expressionP);
+}
+
+
+symbolS *
+md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
+{
+ return NULL;
+}
+
+\f
+/* Turn a string in input_line_pointer into a floating point constant
+ of type TYPE, and store the appropriate bytes in *LITP. The number
+ of LITTLENUMS emitted is stored in *SIZEP. An error message is
+ returned, or NULL on OK. */
+
+const char *
+md_atof (int type, char *litP, int *sizeP)
+{
+ return ieee_md_atof (type, litP, sizeP, FALSE);
+}
--- /dev/null
+/* tc-bpf.h -- Header file for tc-ebpf.c.
+ Copyright (C) 2019 Free Software Foundation, Inc.
+ Contributed by Oracle, Inc.
+
+ This file is part of GAS, the GNU Assembler.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GAS; see the file COPYING. If not, write to the Free
+ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+ 02110-1301, USA. */
+
+#define TC_BPF
+
+#define LISTING_HEADER "BPF GAS "
+
+/* The target BFD architecture. */
+#define TARGET_ARCH bfd_arch_bpf
+#define TARGET_MACH 0 /* The default. */
+
+#define TARGET_FORMAT \
+ (target_big_endian ? "elf64-bpfbe" : "elf64-bpfle")
+
+/* This is used to set the default value for `target_big_endian'. */
+#ifndef TARGET_BYTES_BIG_ENDIAN
+#define TARGET_BYTES_BIG_ENDIAN 0
+#endif
+
+/* .-foo gets turned into PC relative relocs. */
+#define DIFF_EXPR_OK 1
+#define GAS_CGEN_PCREL_R_TYPE(R_TYPE) gas_cgen_pcrel_r_type (R_TYPE)
+
+/* Call md_pcrel_from_section(), not md_pcrel_from(). */
+#define MD_PCREL_FROM_SECTION(FIXP, SEC) md_pcrel_from_section (FIXP, SEC)
+extern long md_pcrel_from_section (struct fix *, segT);
+
+/* We don't need to handle .word strangely. */
+#define WORKING_DOT_WORD
+
+/* Values passed to md_apply_fix don't include the symbol value. */
+#define MD_APPLY_SYM_VALUE(FIX) 0
+
docdir
oldincludedir
includedir
+runstatedir
localstatedir
sharedstatedir
sysconfdir
sysconfdir='${prefix}/etc'
sharedstatedir='${prefix}/com'
localstatedir='${prefix}/var'
+runstatedir='${localstatedir}/run'
includedir='${prefix}/include'
oldincludedir='/usr/include'
docdir='${datarootdir}/doc/${PACKAGE_TARNAME}'
| -silent | --silent | --silen | --sile | --sil)
silent=yes ;;
+ -runstatedir | --runstatedir | --runstatedi | --runstated \
+ | --runstate | --runstat | --runsta | --runst | --runs \
+ | --run | --ru | --r)
+ ac_prev=runstatedir ;;
+ -runstatedir=* | --runstatedir=* | --runstatedi=* | --runstated=* \
+ | --runstate=* | --runstat=* | --runsta=* | --runst=* | --runs=* \
+ | --run=* | --ru=* | --r=*)
+ runstatedir=$ac_optarg ;;
+
-sbindir | --sbindir | --sbindi | --sbind | --sbin | --sbi | --sb)
ac_prev=sbindir ;;
-sbindir=* | --sbindir=* | --sbindi=* | --sbind=* | --sbin=* \
for ac_var in exec_prefix prefix bindir sbindir libexecdir datarootdir \
datadir sysconfdir sharedstatedir localstatedir includedir \
oldincludedir docdir infodir htmldir dvidir pdfdir psdir \
- libdir localedir mandir
+ libdir localedir mandir runstatedir
do
eval ac_val=\$$ac_var
# Remove trailing slashes.
--sysconfdir=DIR read-only single-machine data [PREFIX/etc]
--sharedstatedir=DIR modifiable architecture-independent data [PREFIX/com]
--localstatedir=DIR modifiable single-machine data [PREFIX/var]
+ --runstatedir=DIR modifiable per-process data [LOCALSTATEDIR/run]
--libdir=DIR object code libraries [EPREFIX/lib]
--includedir=DIR C header files [PREFIX/include]
--oldincludedir=DIR C header files for non-gcc [/usr/include]
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <<_LT_EOF
-#line 11346 "configure"
+#line 11358 "configure"
#include "confdefs.h"
#if HAVE_DLFCN_H
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <<_LT_EOF
-#line 11452 "configure"
+#line 11464 "configure"
#include "confdefs.h"
#if HAVE_DLFCN_H
We can't simply define LARGE_OFF_T to be 9223372036854775807,
since some C++ compilers masquerading as C compilers
incorrectly reject 9223372036854775807. */
-#define LARGE_OFF_T (((off_t) 1 << 62) - 1 + ((off_t) 1 << 62))
+#define LARGE_OFF_T ((((off_t) 1 << 31) << 31) - 1 + (((off_t) 1 << 31) << 31))
int off_t_is_large[(LARGE_OFF_T % 2147483629 == 721
&& LARGE_OFF_T % 2147483647 == 1)
? 1 : -1];
We can't simply define LARGE_OFF_T to be 9223372036854775807,
since some C++ compilers masquerading as C compilers
incorrectly reject 9223372036854775807. */
-#define LARGE_OFF_T (((off_t) 1 << 62) - 1 + ((off_t) 1 << 62))
+#define LARGE_OFF_T ((((off_t) 1 << 31) << 31) - 1 + (((off_t) 1 << 31) << 31))
int off_t_is_large[(LARGE_OFF_T % 2147483629 == 721
&& LARGE_OFF_T % 2147483647 == 1)
? 1 : -1];
We can't simply define LARGE_OFF_T to be 9223372036854775807,
since some C++ compilers masquerading as C compilers
incorrectly reject 9223372036854775807. */
-#define LARGE_OFF_T (((off_t) 1 << 62) - 1 + ((off_t) 1 << 62))
+#define LARGE_OFF_T ((((off_t) 1 << 31) << 31) - 1 + (((off_t) 1 << 31) << 31))
int off_t_is_large[(LARGE_OFF_T % 2147483629 == 721
&& LARGE_OFF_T % 2147483647 == 1)
? 1 : -1];
We can't simply define LARGE_OFF_T to be 9223372036854775807,
since some C++ compilers masquerading as C compilers
incorrectly reject 9223372036854775807. */
-#define LARGE_OFF_T (((off_t) 1 << 62) - 1 + ((off_t) 1 << 62))
+#define LARGE_OFF_T ((((off_t) 1 << 31) << 31) - 1 + (((off_t) 1 << 31) << 31))
int off_t_is_large[(LARGE_OFF_T % 2147483629 == 721
&& LARGE_OFF_T % 2147483647 == 1)
? 1 : -1];
We can't simply define LARGE_OFF_T to be 9223372036854775807,
since some C++ compilers masquerading as C compilers
incorrectly reject 9223372036854775807. */
-#define LARGE_OFF_T (((off_t) 1 << 62) - 1 + ((off_t) 1 << 62))
+#define LARGE_OFF_T ((((off_t) 1 << 31) << 31) - 1 + (((off_t) 1 << 31) << 31))
int off_t_is_large[(LARGE_OFF_T % 2147483629 == 721
&& LARGE_OFF_T % 2147483647 == 1)
? 1 : -1];
done
;;
+ bpf)
+ if test $this_target = $target ; then
+
+cat >>confdefs.h <<_ACEOF
+#define DEFAULT_ARCH "${arch}"
+_ACEOF
+
+ fi
+ using_cgen=yes
+ ;;
epiphany | fr30 | ip2k | iq2000 | lm32 | m32r | or1k)
using_cgen=yes
;;
done
;;
+ bpf)
+ if test $this_target = $target ; then
+ AC_DEFINE_UNQUOTED(DEFAULT_ARCH, "${arch}", [Default architecture.])
+ fi
+ using_cgen=yes
+ ;;
epiphany | fr30 | ip2k | iq2000 | lm32 | m32r | or1k)
using_cgen=yes
;;
d30v-*-*) fmt=elf ;;
dlx-*-*) fmt=elf ;;
+ bpf-*-*) fmt=elf ;;
epiphany-*-*) fmt=elf ;;
fr30-*-*) fmt=elf ;;
c-arm.texi \
c-avr.texi \
c-bfin.texi \
+ c-bpf.texi \
c-cr16.texi \
c-cris.texi \
c-csky.texi \
prefix = @prefix@
program_transform_name = @program_transform_name@
psdir = @psdir@
+runstatedir = @runstatedir@
sbindir = @sbindir@
sharedstatedir = @sharedstatedir@
srcdir = @srcdir@
c-arm.texi \
c-avr.texi \
c-bfin.texi \
+ c-bpf.texi \
c-cr16.texi \
c-cris.texi \
c-csky.texi \
@set ARM
@set AVR
@set Blackfin
+@set BPF
@set CR16
@set CRIS
@set CSKY
@ifset Blackfin
@set Blackfin
@end ifset
+@ifset BPF
+@set BPF
+@end ifset
@ifset H8/300
@set H8
@end ifset
[@b{-mno-fdpic}]
[@b{-mnopic}]
@end ifset
+@ifset BPF
+
+@emph{Target BPF options:}
+ [@b{-EL}] [@b{-EB}]
+@end ifset
@ifset CRIS
@emph{Target CRIS options:}
@end ifset
+@ifset BPF
+
+@ifclear man
+@xref{BPF Options}, for the options available when @value{AS} is
+configured for the Linux kernel BPF processor family.
+@end ifclear
+
+@ifset man
+@c man begin OPTIONS
+The following options are available when @value{AS} is configured for
+the Linux kernel BPF processor family.
+@c man end
+@c man begin INCLUDE
+@include c-bpf.texi
+@c ended inside the included file
+@end ifset
+
+@end ifset
+
@c man begin OPTIONS
@ifset CRIS
See the info pages for documentation of the CRIS-specific options.
@ifset Blackfin
* Blackfin-Dependent:: Blackfin Dependent Features
@end ifset
+@ifset BPF
+* BPF-Dependent:: BPF Dependent Features
+@end ifset
@ifset CR16
* CR16-Dependent:: CR16 Dependent Features
@end ifset
@include c-bfin.texi
@end ifset
+@ifset BPF
+@include c-bpf.texi
+@end ifset
+
@ifset CR16
@include c-cr16.texi
@end ifset
--- /dev/null
+@c Copyright (C) 2019 Free Software Foundation, Inc.
+@c This is part of the GAS manual.
+@c For copying conditions, see the file as.texinfo.
+
+@ifset GENERIC
+@page
+@node BPF-Dependent
+@chapter BPF Dependent Features
+@end ifset
+
+@ifclear GENERIC
+@node Machine Dependencies
+@chapter BPF Dependent Features
+@end ifclear
+
+@cindex BPF support
+@menu
+* BPF Options:: Options
+* BPF Syntax:: Syntax
+* BPF Opcodes:: Opcodes
+@end menu
+
+@node BPF Options
+@section Options
+@cindex BPF options (none)
+@cindex options for BPF (none)
+
+@c man begin OPTIONS
+@table @gcctabopt
+
+@cindex @option{-EB} command-line option, BPF
+@item -EB
+This option specifies that the assembler should emit big-endian eBPF.
+
+@cindex @option{-EL} command-line option, BPF
+@item -EL
+This option specifies that the assembler should emit little-endian
+eBPF.
+@end table
+
+Note that if no endianness option is specified in the command line,
+the host endianness is used.
+@c man end
+
+@node BPF Syntax
+@section Syntax
+@menu
+* BPF-Chars:: Special Characters
+* BPF-Regs:: Register Names
+* BPF-Pseudo-Maps:: Pseudo map fds
+@end menu
+
+@node BPF-Chars
+@subsection Special Characters
+
+@cindex line comment character, BPF
+@cindex BPF line comment character
+The presence of a @samp{;} on a line indicates the start of a comment
+that extends to the end of the current line. If a @samp{#} appears as
+the first character of a line, the whole line is treated as a comment.
+
+@cindex statement separator, BPF
+Statements and assembly directives are separated by newlines.
+
+@node BPF-Regs
+@subsection Register Names
+
+@cindex BPF register names
+@cindex register names, BPF
+The eBPF processor provides ten general-purpose 64-bit registers,
+which are read-write, and a read-only frame pointer register:
+
+@table @samp
+@item %r0 .. %r9
+General-purpose registers.
+@item %r10
+Frame pointer register.
+@end table
+
+Some registers have additional names, to reflect their role in the
+eBPF ABI:
+
+@table @samp
+@item %a
+This is @samp{%r0}.
+@item %ctx
+This is @samp{%r6}.
+@item %fp
+This is @samp{%r10}.
+@end table
+
+@node BPF-Pseudo-Maps
+@subsection Pseudo Maps
+
+@cindex pseudo map fd, BPF
+The @samp{LDDW} instruction can take a literal pseudo map file
+descriptor as its second argument. This uses the syntax
+@samp{%map_fd(N)} where @samp{N} is a signed number.
+
+For example, to load the address of the pseudo map with file
+descriptor @samp{2} in register @samp{r1} we would do:
+
+@smallexample
+ lddw %r1, %map_fd(2)
+@end smallexample
+
+@node BPF Opcodes
+@section Opcodes
+
+@cindex BPF opcodes
+@cindex opcodes for BPF
+In the instruction descriptions below the following field descriptors
+are used:
+
+@table @code
+@item %d
+Destination general-purpose register whose role is to be destination
+of an operation.
+@item %s
+Source general-purpose register whose role is to be the source of an
+operation.
+@item disp16
+16-bit signed PC-relative offset, measured in number of 64-bit words,
+minus one.
+@item disp32
+32-bit signed PC-relative offset, measured in number of 64-bit words,
+minus one.
+@item offset16
+Signed 16-bit immediate.
+@item imm32
+Signed 32-bit immediate.
+@item imm64
+Signed 64-bit immediate.
+@end table
+
+@subsubsection Arithmetic instructions
+
+The destination register in these instructions act like an
+accumulator.
+
+@table @code
+@item add %d, (%s|imm32)
+64-bit arithmetic addition.
+@item sub %d, (%s|imm32)
+64-bit arithmetic subtraction.
+@item mul %d, (%s|imm32)
+64-bit arithmetic multiplication.
+@item div %d, (%s|imm32)
+64-bit arithmetic integer division.
+@item mod %d, (%s|imm32)
+64-bit integer remainder.
+@item and %d, (%s|imm32)
+64-bit bit-wise ``and'' operation.
+@item or %d, (%s|imm32)
+64-bit bit-wise ``or'' operation.
+@item xor %d, (%s|imm32)
+64-bit bit-wise exclusive-or operation.
+@item lsh %d, (%s|imm32)
+64-bit left shift, by @code{%s} or @code{imm32} bits.
+@item rsh %d, (%s|imm32)
+64-bit right logical shift, by @code{%s} or @code{imm32} bits.
+@item arsh %d, (%s|imm32)
+64-bit right arithmetic shift, by @code{%s} or @code{imm32} bits.
+@item neg %d
+64-bit arithmetic negation.
+@item mov %d, (%s|imm32)
+Move the 64-bit value of @code{%s} in @code{%d}, or load @code{imm32}
+in @code{%d}.
+@end table
+
+@subsubsection 32-bit arithmetic instructions
+
+The destination register in these instructions act as an accumulator.
+
+@table @code
+@item add32 %d, (%s|imm32)
+32-bit arithmetic addition.
+@item sub32 %d, (%s|imm32)
+32-bit arithmetic subtraction.
+@item mul32 %d, (%s|imm32)
+32-bit arithmetic multiplication.
+@item div32 %d, (%s|imm32)
+32-bit arithmetic integer division.
+@item mod32 %d, (%s|imm32)
+32-bit integer remainder.
+@item and32 %d, (%s|imm32)
+32-bit bit-wise ``and'' operation.
+@item or32 %d, (%s|imm32)
+32-bit bit-wise ``or'' operation.
+@item xor32 %d, (%s|imm32)
+32-bit bit-wise exclusive-or operation.
+@item lsh32 %d, (%s|imm32)
+32-bit left shift, by @code{%s} or @code{imm32} bits.
+@item rsh32 %d, (%s|imm32)
+32-bit right logical shift, by @code{%s} or @code{imm32} bits.
+@item arsh32 %d, (%s|imm32)
+32-bit right arithmetic shift, by @code{%s} or @code{imm32} bits.
+@item neg32 %d
+32-bit arithmetic negation.
+@item mov32 %d, (%s|imm32)
+Move the 32-bit value of @code{%s} in @code{%d}, or load @code{imm32}
+in @code{%d}.
+@end table
+
+@subsubsection Endianness conversion instructions
+
+@table @code
+@item endle %d, (8|16|32)
+Convert the 8-bit, 16-bit or 32-bit value in @code{%d} to
+little-endian.
+@item endbe %d, (8|16|32)
+Convert the 8-bit, 16-bit or 32-bit value in @code{%d} to big-endian.
+@end table
+
+@subsubsection 64-bit load and pseudo maps
+
+@table @code
+@item lddw %d, imm64
+Load the given signed 64-bit immediate, or pseudo map descriptor, to
+the destination register @code{%d}.
+@item lddw %d, %map_fd(N)
+Load the address of the given pseudo map fd @emph{N} to the
+destination register @code{%d}.
+@end table
+
+@subsubsection Load instructions for socket filters
+
+The following instructions are intended to be used in socket filters,
+and are therefore not general-purpose: they make assumptions on the
+contents of several registers. See the file
+@file{Documentation/networking/filter.txt} in the Linux kernel source
+tree for more information.
+
+Absolute loads:
+
+@table @code
+@item ldabsdw %d, %s, imm32
+Absolute 64-bit load.
+@item ldabsw %d, %s, imm32
+Absolute 32-bit load.
+@item ldabsh %d, %s, imm32
+Absolute 16-bit load.
+@item ldabsb %d, %s, imm32
+Absolute 8-bit load.
+@end table
+
+Indirect loads:
+
+@table @code
+@item ldinddw %d, %s, imm32
+Indirect 64-bit load.
+@item ldindw %d, %s, imm32
+Indirect 32-bit load.
+@item ldindh %d, %s, imm32
+Indirect 16-bit load.
+@item ldindb %d, %s, imm32
+Indirect 8-bit load.
+@end table
+
+@subsubsection Generic load/store instructions
+
+General-purpose load and store instructions are provided for several
+word sizes.
+
+Load to register instructions:
+
+@table @code
+@item ldxdw %d, [%s+offset16]
+Generic 64-bit load.
+@item ldxw %d, [%s+offset16]
+Generic 32-bit load.
+@item ldxh %d, [%s+offset16]
+Generic 16-bit load.
+@item ldxb %d, [%s+offset16]
+Generic 8-bit load.
+@end table
+
+Store from register instructions:
+
+@table @code
+@item stxdw [%d+offset16], %s
+Generic 64-bit store.
+@item stxw [%d+offset16], %s
+Generic 32-bit store.
+@item stxh [%d+offset16], %s
+Generic 16-bit store.
+@item stxb [%d+offset16], %s
+Generic 8-bit store.
+@end table
+
+Store from immediates instructions:
+
+@table @code
+@item stddw [%d+offset16], imm32
+Store immediate as 64-bit.
+@item stdw [%d+offset16], imm32
+Store immediate as 32-bit.
+@item stdh [%d+offset16], imm32
+Store immediate as 16-bit.
+@item stdb [%d+offset16], imm32
+Store immediate as 8-bit.
+@end table
+
+@subsubsection Jump instructions
+
+eBPF provides the following compare-and-jump instructions, which
+compare the values of the two given registers, or the values of a
+register and an immediate, and perform a branch in case the comparison
+holds true.
+
+@table @code
+@item ja %d,(%s|imm32),disp16
+Jump-always.
+@item jeq %d,(%s|imm32),disp16
+Jump if equal.
+@item jgt %d,(%s|imm32),disp16
+Jump if greater.
+@item jge %d,(%s|imm32),disp16
+Jump if greater or equal.
+@item jlt %d,(%s|imm32),disp16
+Jump if lesser.
+@item jle %d,(%s|imm32),disp16
+Jump if lesser or equal.
+@item jset %d,(%s|imm32),disp16
+Jump if signed equal.
+@item jne %d,(%s|imm32),disp16
+Jump if not equal.
+@item jsgt %d,(%s|imm32),disp16
+Jump if signed greater.
+@item jsge %d,(%s|imm32),disp16
+Jump if signed greater or equal.
+@item jslt %d,(%s|imm32),disp16
+Jump if signed lesser.
+@item jsle %d,(%s|imm32),disp16
+Jump if signed lesser or equal.
+@end table
+
+A call instruction is provided in order to perform calls to other eBPF
+functions, or to external kernel helpers:
+
+@table @code
+@item call (disp32|imm32)
+Jump and link to the offset @emph{disp32}, or to the kernel helper
+function identified by @emph{imm32}.
+@end table
+
+Finally:
+
+@table @code
+@item exit
+Terminate the eBPF program.
+@end table
+
+@subsubsection Atomic instructions
+
+Atomic exchange-and-add instructions are provided in two flavors: one
+for swapping 64-bit quantities and another for 32-bit quantities.
+
+@table @code
+@item xadddw [%d+offset16],%s
+Exchange-and-add a 64-bit value at the specified location.
+@item xaddw [%d+offset16],%s
+Exchange-and-add a 32-bit value at the specified location.
+@end table
# Set $nop_type appropriately to indicate the NOP instruction mnemonic.
case $target_triplet in {
+ { "bpf-*-*" } {
+ set nop_type 6
+ }
{ "mmix-*-*" } {
set nop_type 5
}
.*: Assembler messages:
-.*:22: Error: attempt to move \.org backwards
+.*:24: Error: attempt to move \.org backwards
mov g0, g0
.elseif nop_type == 5
set $0, $0
+ .elseif nop_type == 6
+ mov %r1,%r1
.else
nop
.endif
--- /dev/null
+#as: --EB
+#source: alu.s
+#objdump: -dr
+#name: eBPF ALU64 instructions, big endian
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: 07 20 00 00 00 00 02 9a add %r2,0x29a
+ 8: 07 30 00 00 ff ff fd 66 add %r3,-666
+ 10: 07 40 00 00 7e ad be ef add %r4,0x7eadbeef
+ 18: 0f 56 00 00 00 00 00 00 add %r5,%ctx
+ 20: 17 20 00 00 00 00 02 9a sub %r2,0x29a
+ 28: 17 30 00 00 ff ff fd 66 sub %r3,-666
+ 30: 17 40 00 00 7e ad be ef sub %r4,0x7eadbeef
+ 38: 1f 56 00 00 00 00 00 00 sub %r5,%ctx
+ 40: 27 20 00 00 00 00 02 9a mul %r2,0x29a
+ 48: 27 30 00 00 ff ff fd 66 mul %r3,-666
+ 50: 27 40 00 00 7e ad be ef mul %r4,0x7eadbeef
+ 58: 2f 56 00 00 00 00 00 00 mul %r5,%ctx
+ 60: 37 20 00 00 00 00 02 9a div %r2,0x29a
+ 68: 37 30 00 00 ff ff fd 66 div %r3,-666
+ 70: 37 40 00 00 7e ad be ef div %r4,0x7eadbeef
+ 78: 3f 56 00 00 00 00 00 00 div %r5,%ctx
+ 80: 47 20 00 00 00 00 02 9a or %r2,0x29a
+ 88: 47 30 00 00 ff ff fd 66 or %r3,-666
+ 90: 47 40 00 00 7e ad be ef or %r4,0x7eadbeef
+ 98: 4f 56 00 00 00 00 00 00 or %r5,%ctx
+ a0: 57 20 00 00 00 00 02 9a and %r2,0x29a
+ a8: 57 30 00 00 ff ff fd 66 and %r3,-666
+ b0: 57 40 00 00 7e ad be ef and %r4,0x7eadbeef
+ b8: 5f 56 00 00 00 00 00 00 and %r5,%ctx
+ c0: 67 20 00 00 00 00 02 9a lsh %r2,0x29a
+ c8: 67 30 00 00 ff ff fd 66 lsh %r3,-666
+ d0: 67 40 00 00 7e ad be ef lsh %r4,0x7eadbeef
+ d8: 6f 56 00 00 00 00 00 00 lsh %r5,%ctx
+ e0: 77 20 00 00 00 00 02 9a rsh %r2,0x29a
+ e8: 77 30 00 00 ff ff fd 66 rsh %r3,-666
+ f0: 77 40 00 00 7e ad be ef rsh %r4,0x7eadbeef
+ f8: 7f 56 00 00 00 00 00 00 rsh %r5,%ctx
+ 100: 97 20 00 00 00 00 02 9a mod %r2,0x29a
+ 108: 97 30 00 00 ff ff fd 66 mod %r3,-666
+ 110: 97 40 00 00 7e ad be ef mod %r4,0x7eadbeef
+ 118: 9f 56 00 00 00 00 00 00 mod %r5,%ctx
+ 120: a7 20 00 00 00 00 02 9a xor %r2,0x29a
+ 128: a7 30 00 00 ff ff fd 66 xor %r3,-666
+ 130: a7 40 00 00 7e ad be ef xor %r4,0x7eadbeef
+ 138: af 56 00 00 00 00 00 00 xor %r5,%ctx
+ 140: b7 20 00 00 00 00 02 9a mov %r2,0x29a
+ 148: b7 30 00 00 ff ff fd 66 mov %r3,-666
+ 150: b7 40 00 00 7e ad be ef mov %r4,0x7eadbeef
+ 158: bf 56 00 00 00 00 00 00 mov %r5,%ctx
+ 160: c7 20 00 00 00 00 02 9a arsh %r2,0x29a
+ 168: c7 30 00 00 ff ff fd 66 arsh %r3,-666
+ 170: c7 40 00 00 7e ad be ef arsh %r4,0x7eadbeef
+ 178: cf 56 00 00 00 00 00 00 arsh %r5,%ctx
+ 180: 8f 20 00 00 00 00 00 00 neg %r2
--- /dev/null
+#as: --EL
+#objdump: -dr
+#name: eBPF ALU64 instructions
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: 07 02 00 00 9a 02 00 00 add %r2,0x29a
+ 8: 07 03 00 00 66 fd ff ff add %r3,-666
+ 10: 07 04 00 00 ef be ad 7e add %r4,0x7eadbeef
+ 18: 0f 65 00 00 00 00 00 00 add %r5,%ctx
+ 20: 17 02 00 00 9a 02 00 00 sub %r2,0x29a
+ 28: 17 03 00 00 66 fd ff ff sub %r3,-666
+ 30: 17 04 00 00 ef be ad 7e sub %r4,0x7eadbeef
+ 38: 1f 65 00 00 00 00 00 00 sub %r5,%ctx
+ 40: 27 02 00 00 9a 02 00 00 mul %r2,0x29a
+ 48: 27 03 00 00 66 fd ff ff mul %r3,-666
+ 50: 27 04 00 00 ef be ad 7e mul %r4,0x7eadbeef
+ 58: 2f 65 00 00 00 00 00 00 mul %r5,%ctx
+ 60: 37 02 00 00 9a 02 00 00 div %r2,0x29a
+ 68: 37 03 00 00 66 fd ff ff div %r3,-666
+ 70: 37 04 00 00 ef be ad 7e div %r4,0x7eadbeef
+ 78: 3f 65 00 00 00 00 00 00 div %r5,%ctx
+ 80: 47 02 00 00 9a 02 00 00 or %r2,0x29a
+ 88: 47 03 00 00 66 fd ff ff or %r3,-666
+ 90: 47 04 00 00 ef be ad 7e or %r4,0x7eadbeef
+ 98: 4f 65 00 00 00 00 00 00 or %r5,%ctx
+ a0: 57 02 00 00 9a 02 00 00 and %r2,0x29a
+ a8: 57 03 00 00 66 fd ff ff and %r3,-666
+ b0: 57 04 00 00 ef be ad 7e and %r4,0x7eadbeef
+ b8: 5f 65 00 00 00 00 00 00 and %r5,%ctx
+ c0: 67 02 00 00 9a 02 00 00 lsh %r2,0x29a
+ c8: 67 03 00 00 66 fd ff ff lsh %r3,-666
+ d0: 67 04 00 00 ef be ad 7e lsh %r4,0x7eadbeef
+ d8: 6f 65 00 00 00 00 00 00 lsh %r5,%ctx
+ e0: 77 02 00 00 9a 02 00 00 rsh %r2,0x29a
+ e8: 77 03 00 00 66 fd ff ff rsh %r3,-666
+ f0: 77 04 00 00 ef be ad 7e rsh %r4,0x7eadbeef
+ f8: 7f 65 00 00 00 00 00 00 rsh %r5,%ctx
+ 100: 97 02 00 00 9a 02 00 00 mod %r2,0x29a
+ 108: 97 03 00 00 66 fd ff ff mod %r3,-666
+ 110: 97 04 00 00 ef be ad 7e mod %r4,0x7eadbeef
+ 118: 9f 65 00 00 00 00 00 00 mod %r5,%ctx
+ 120: a7 02 00 00 9a 02 00 00 xor %r2,0x29a
+ 128: a7 03 00 00 66 fd ff ff xor %r3,-666
+ 130: a7 04 00 00 ef be ad 7e xor %r4,0x7eadbeef
+ 138: af 65 00 00 00 00 00 00 xor %r5,%ctx
+ 140: b7 02 00 00 9a 02 00 00 mov %r2,0x29a
+ 148: b7 03 00 00 66 fd ff ff mov %r3,-666
+ 150: b7 04 00 00 ef be ad 7e mov %r4,0x7eadbeef
+ 158: bf 65 00 00 00 00 00 00 mov %r5,%ctx
+ 160: c7 02 00 00 9a 02 00 00 arsh %r2,0x29a
+ 168: c7 03 00 00 66 fd ff ff arsh %r3,-666
+ 170: c7 04 00 00 ef be ad 7e arsh %r4,0x7eadbeef
+ 178: cf 65 00 00 00 00 00 00 arsh %r5,%ctx
+ 180: 8f 02 00 00 00 00 00 00 neg %r2
--- /dev/null
+# Tests for the ALU64 eBPF instructions
+ .text
+ add %r2, 666
+ add %r3, -666
+ add %r4, 0x7eadbeef
+ add %r5, %r6
+ sub %r2, 666
+ sub %r3, -666
+ sub %r4, 0x7eadbeef
+ sub %r5, %r6
+ mul %r2, 666
+ mul %r3, -666
+ mul %r4, 0x7eadbeef
+ mul %r5, %r6
+ div %r2, 666
+ div %r3, -666
+ div %r4, 0x7eadbeef
+ div %r5, %r6
+ or %r2, 666
+ or %r3, -666
+ or %r4, 0x7eadbeef
+ or %r5, %r6
+ and %r2, 666
+ and %r3, -666
+ and %r4, 0x7eadbeef
+ and %r5, %r6
+ lsh %r2, 666
+ lsh %r3, -666
+ lsh %r4, 0x7eadbeef
+ lsh %r5, %r6
+ rsh %r2, 666
+ rsh %r3, -666
+ rsh %r4, 0x7eadbeef
+ rsh %r5, %r6
+ mod %r2, 666
+ mod %r3, -666
+ mod %r4, 0x7eadbeef
+ mod %r5, %r6
+ xor %r2, 666
+ xor %r3, -666
+ xor %r4, 0x7eadbeef
+ xor %r5, %r6
+ mov %r2, 666
+ mov %r3, -666
+ mov %r4, 0x7eadbeef
+ mov %r5, %r6
+ arsh %r2, 666
+ arsh %r3, -666
+ arsh %r4, 0x7eadbeef
+ arsh %r5, %r6
+ neg %r2
--- /dev/null
+#as: --EB
+#source: alu32.s
+#objdump: -dr
+#name: eBPF ALU instructions, big-endian
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: 04 20 00 00 00 00 02 9a add32 %r2,0x29a
+ 8: 04 30 00 00 ff ff fd 66 add32 %r3,-666
+ 10: 04 40 00 00 7e ad be ef add32 %r4,0x7eadbeef
+ 18: 0c 56 00 00 00 00 00 00 add32 %r5,%ctx
+ 20: 14 20 00 00 00 00 02 9a sub32 %r2,0x29a
+ 28: 14 30 00 00 ff ff fd 66 sub32 %r3,-666
+ 30: 14 40 00 00 7e ad be ef sub32 %r4,0x7eadbeef
+ 38: 1c 56 00 00 00 00 00 00 sub32 %r5,%ctx
+ 40: 24 20 00 00 00 00 02 9a mul32 %r2,0x29a
+ 48: 24 30 00 00 ff ff fd 66 mul32 %r3,-666
+ 50: 24 40 00 00 7e ad be ef mul32 %r4,0x7eadbeef
+ 58: 2c 56 00 00 00 00 00 00 mul32 %r5,%ctx
+ 60: 34 20 00 00 00 00 02 9a div32 %r2,0x29a
+ 68: 34 30 00 00 ff ff fd 66 div32 %r3,-666
+ 70: 34 40 00 00 7e ad be ef div32 %r4,0x7eadbeef
+ 78: 3c 56 00 00 00 00 00 00 div32 %r5,%ctx
+ 80: 44 20 00 00 00 00 02 9a or32 %r2,0x29a
+ 88: 44 30 00 00 ff ff fd 66 or32 %r3,-666
+ 90: 44 40 00 00 7e ad be ef or32 %r4,0x7eadbeef
+ 98: 4c 56 00 00 00 00 00 00 or32 %r5,%ctx
+ a0: 54 20 00 00 00 00 02 9a and32 %r2,0x29a
+ a8: 54 30 00 00 ff ff fd 66 and32 %r3,-666
+ b0: 54 40 00 00 7e ad be ef and32 %r4,0x7eadbeef
+ b8: 5c 56 00 00 00 00 00 00 and32 %r5,%ctx
+ c0: 64 20 00 00 00 00 02 9a lsh32 %r2,0x29a
+ c8: 64 30 00 00 ff ff fd 66 lsh32 %r3,-666
+ d0: 64 40 00 00 7e ad be ef lsh32 %r4,0x7eadbeef
+ d8: 6c 56 00 00 00 00 00 00 lsh32 %r5,%ctx
+ e0: 74 20 00 00 00 00 02 9a rsh32 %r2,0x29a
+ e8: 74 30 00 00 ff ff fd 66 rsh32 %r3,-666
+ f0: 74 40 00 00 7e ad be ef rsh32 %r4,0x7eadbeef
+ f8: 7c 56 00 00 00 00 00 00 rsh32 %r5,%ctx
+ 100: 94 20 00 00 00 00 02 9a mod32 %r2,0x29a
+ 108: 94 30 00 00 ff ff fd 66 mod32 %r3,-666
+ 110: 94 40 00 00 7e ad be ef mod32 %r4,0x7eadbeef
+ 118: 9c 56 00 00 00 00 00 00 mod32 %r5,%ctx
+ 120: a4 20 00 00 00 00 02 9a xor32 %r2,0x29a
+ 128: a4 30 00 00 ff ff fd 66 xor32 %r3,-666
+ 130: a4 40 00 00 7e ad be ef xor32 %r4,0x7eadbeef
+ 138: ac 56 00 00 00 00 00 00 xor32 %r5,%ctx
+ 140: b4 20 00 00 00 00 02 9a mov32 %r2,0x29a
+ 148: b4 30 00 00 ff ff fd 66 mov32 %r3,-666
+ 150: b4 40 00 00 7e ad be ef mov32 %r4,0x7eadbeef
+ 158: bc 56 00 00 00 00 00 00 mov32 %r5,%ctx
+ 160: c4 20 00 00 00 00 02 9a arsh32 %r2,0x29a
+ 168: c4 30 00 00 ff ff fd 66 arsh32 %r3,-666
+ 170: c4 40 00 00 7e ad be ef arsh32 %r4,0x7eadbeef
+ 178: cc 56 00 00 00 00 00 00 arsh32 %r5,%ctx
+ 180: 8c 20 00 00 00 00 00 00 neg32 %r2
+ 188: d4 90 00 00 00 00 00 10 endle %r9,16
+ 190: d4 80 00 00 00 00 00 20 endle %r8,32
+ 198: d4 70 00 00 00 00 00 40 endle %r7,64
+ 1a0: dc 60 00 00 00 00 00 10 endbe %ctx,16
+ 1a8: dc 50 00 00 00 00 00 20 endbe %r5,32
+ 1b0: dc 40 00 00 00 00 00 40 endbe %r4,64
--- /dev/null
+#as: --EL
+#objdump: -dr
+#name: eBPF ALU instructions
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: 04 02 00 00 9a 02 00 00 add32 %r2,0x29a
+ 8: 04 03 00 00 66 fd ff ff add32 %r3,-666
+ 10: 04 04 00 00 ef be ad 7e add32 %r4,0x7eadbeef
+ 18: 0c 65 00 00 00 00 00 00 add32 %r5,%ctx
+ 20: 14 02 00 00 9a 02 00 00 sub32 %r2,0x29a
+ 28: 14 03 00 00 66 fd ff ff sub32 %r3,-666
+ 30: 14 04 00 00 ef be ad 7e sub32 %r4,0x7eadbeef
+ 38: 1c 65 00 00 00 00 00 00 sub32 %r5,%ctx
+ 40: 24 02 00 00 9a 02 00 00 mul32 %r2,0x29a
+ 48: 24 03 00 00 66 fd ff ff mul32 %r3,-666
+ 50: 24 04 00 00 ef be ad 7e mul32 %r4,0x7eadbeef
+ 58: 2c 65 00 00 00 00 00 00 mul32 %r5,%ctx
+ 60: 34 02 00 00 9a 02 00 00 div32 %r2,0x29a
+ 68: 34 03 00 00 66 fd ff ff div32 %r3,-666
+ 70: 34 04 00 00 ef be ad 7e div32 %r4,0x7eadbeef
+ 78: 3c 65 00 00 00 00 00 00 div32 %r5,%ctx
+ 80: 44 02 00 00 9a 02 00 00 or32 %r2,0x29a
+ 88: 44 03 00 00 66 fd ff ff or32 %r3,-666
+ 90: 44 04 00 00 ef be ad 7e or32 %r4,0x7eadbeef
+ 98: 4c 65 00 00 00 00 00 00 or32 %r5,%ctx
+ a0: 54 02 00 00 9a 02 00 00 and32 %r2,0x29a
+ a8: 54 03 00 00 66 fd ff ff and32 %r3,-666
+ b0: 54 04 00 00 ef be ad 7e and32 %r4,0x7eadbeef
+ b8: 5c 65 00 00 00 00 00 00 and32 %r5,%ctx
+ c0: 64 02 00 00 9a 02 00 00 lsh32 %r2,0x29a
+ c8: 64 03 00 00 66 fd ff ff lsh32 %r3,-666
+ d0: 64 04 00 00 ef be ad 7e lsh32 %r4,0x7eadbeef
+ d8: 6c 65 00 00 00 00 00 00 lsh32 %r5,%ctx
+ e0: 74 02 00 00 9a 02 00 00 rsh32 %r2,0x29a
+ e8: 74 03 00 00 66 fd ff ff rsh32 %r3,-666
+ f0: 74 04 00 00 ef be ad 7e rsh32 %r4,0x7eadbeef
+ f8: 7c 65 00 00 00 00 00 00 rsh32 %r5,%ctx
+ 100: 94 02 00 00 9a 02 00 00 mod32 %r2,0x29a
+ 108: 94 03 00 00 66 fd ff ff mod32 %r3,-666
+ 110: 94 04 00 00 ef be ad 7e mod32 %r4,0x7eadbeef
+ 118: 9c 65 00 00 00 00 00 00 mod32 %r5,%ctx
+ 120: a4 02 00 00 9a 02 00 00 xor32 %r2,0x29a
+ 128: a4 03 00 00 66 fd ff ff xor32 %r3,-666
+ 130: a4 04 00 00 ef be ad 7e xor32 %r4,0x7eadbeef
+ 138: ac 65 00 00 00 00 00 00 xor32 %r5,%ctx
+ 140: b4 02 00 00 9a 02 00 00 mov32 %r2,0x29a
+ 148: b4 03 00 00 66 fd ff ff mov32 %r3,-666
+ 150: b4 04 00 00 ef be ad 7e mov32 %r4,0x7eadbeef
+ 158: bc 65 00 00 00 00 00 00 mov32 %r5,%ctx
+ 160: c4 02 00 00 9a 02 00 00 arsh32 %r2,0x29a
+ 168: c4 03 00 00 66 fd ff ff arsh32 %r3,-666
+ 170: c4 04 00 00 ef be ad 7e arsh32 %r4,0x7eadbeef
+ 178: cc 65 00 00 00 00 00 00 arsh32 %r5,%ctx
+ 180: 8c 02 00 00 00 00 00 00 neg32 %r2
+ 188: d4 09 00 00 10 00 00 00 endle %r9,16
+ 190: d4 08 00 00 20 00 00 00 endle %r8,32
+ 198: d4 07 00 00 40 00 00 00 endle %r7,64
+ 1a0: dc 06 00 00 10 00 00 00 endbe %ctx,16
+ 1a8: dc 05 00 00 20 00 00 00 endbe %r5,32
+ 1b0: dc 04 00 00 40 00 00 00 endbe %r4,64
--- /dev/null
+# Tests for the ALU eBPF instructions
+ .text
+ add32 %r2, 666
+ add32 %r3, -666
+ add32 %r4, 0x7eadbeef
+ add32 %r5, %r6
+ sub32 %r2, 666
+ sub32 %r3, -666
+ sub32 %r4, 0x7eadbeef
+ sub32 %r5, %r6
+ mul32 %r2, 666
+ mul32 %r3, -666
+ mul32 %r4, 0x7eadbeef
+ mul32 %r5, %r6
+ div32 %r2, 666
+ div32 %r3, -666
+ div32 %r4, 0x7eadbeef
+ div32 %r5, %r6
+ or32 %r2, 666
+ or32 %r3, -666
+ or32 %r4, 0x7eadbeef
+ or32 %r5, %r6
+ and32 %r2, 666
+ and32 %r3, -666
+ and32 %r4, 0x7eadbeef
+ and32 %r5, %r6
+ lsh32 %r2, 666
+ lsh32 %r3, -666
+ lsh32 %r4, 0x7eadbeef
+ lsh32 %r5, %r6
+ rsh32 %r2, 666
+ rsh32 %r3, -666
+ rsh32 %r4, 0x7eadbeef
+ rsh32 %r5, %r6
+ mod32 %r2, 666
+ mod32 %r3, -666
+ mod32 %r4, 0x7eadbeef
+ mod32 %r5, %r6
+ xor32 %r2, 666
+ xor32 %r3, -666
+ xor32 %r4, 0x7eadbeef
+ xor32 %r5, %r6
+ mov32 %r2, 666
+ mov32 %r3, -666
+ mov32 %r4, 0x7eadbeef
+ mov32 %r5, %r6
+ arsh32 %r2, 666
+ arsh32 %r3, -666
+ arsh32 %r4, 0x7eadbeef
+ arsh32 %r5, %r6
+ neg32 %r2
+ endle %r9,16
+ endle %r8,32
+ endle %r7,64
+ endbe %r6,16
+ endbe %r5,32
+ endbe %r4,64
--- /dev/null
+#as: --EB
+#source: atomic.s
+#objdump: -dr
+#name: eBPF atomic instructions, big endian
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: db 12 1e ef 00 00 00 00 xadddw \[%r1\+0x1eef\],%r2
+ 8: c3 12 1e ef 00 00 00 00 xaddw \[%r1\+0x1eef\],%r2
--- /dev/null
+#as: --EL
+#objdump: -dr
+#name: eBPF atomic instructions
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: db 21 ef 1e 00 00 00 00 xadddw \[%r1\+0x1eef\],%r2
+ 8: c3 21 ef 1e 00 00 00 00 xaddw \[%r1\+0x1eef\],%r2
--- /dev/null
+ # Test for eBPF ADDW and ADDDW instructions
+ .text
+ xadddw [%r1+0x1eef], %r2
+ xaddw [%r1+0x1eef], %r2
+
--- /dev/null
+# GAS testsuite for the Linux eBPF -*- Tcl -*-
+#
+# Copyright (C) 2019 Free Software Foundation, Inc.
+# Contributed by Oracle, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+if {[istarget bpf*-*-*]} {
+ run_dump_test lddw
+ run_dump_test alu
+ run_dump_test alu32
+ run_dump_test mem
+ run_dump_test jump
+ run_dump_test call
+ run_dump_test exit
+ run_dump_test atomic
+
+ run_dump_test lddw-be
+ run_dump_test alu-be
+ run_dump_test alu32-be
+ run_dump_test mem-be
+ run_dump_test jump-be
+ run_dump_test call-be
+ run_dump_test exit-be
+ run_dump_test atomic-be
+}
--- /dev/null
+#as: --EB
+#source: call.s
+#objdump: -dr
+#name: eBPF CALL instruction, big endian
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+[0-9a-f]+ <.*>:
+ 0: 85 00 00 00 00 00 00 00 call 0
+ 8: 85 00 00 00 00 00 00 01 call 1
+ 10: 85 00 00 00 ff ff ff fe call -2
+ 18: 85 00 00 00 00 00 00 0a call 10
+ 20: 85 01 00 00 00 00 00 00 call 0
+[0-9a-f]+ <foo>:
+ 28: 85 01 00 00 ff ff ff ff call -1
+ 30: 85 01 00 00 ff ff ff fe call -2
+ 38: 85 01 00 00 ff ff ff fd call -3
\ No newline at end of file
--- /dev/null
+#as: --EL
+#objdump: -dr
+#name: eBPF CALL instruction
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+[0-9a-f]+ <.*>:
+ 0: 85 00 00 00 00 00 00 00 call 0
+ 8: 85 00 00 00 01 00 00 00 call 1
+ 10: 85 00 00 00 fe ff ff ff call -2
+ 18: 85 00 00 00 0a 00 00 00 call 10
+ 20: 85 10 00 00 00 00 00 00 call 0
+[0-9a-f]+ <foo>:
+ 28: 85 10 00 00 ff ff ff ff call -1
+ 30: 85 10 00 00 fe ff ff ff call -2
+ 38: 85 10 00 00 fd ff ff ff call -3
--- /dev/null
+ # eBPF tests for the CALL instruction
+
+ .text
+ call 0
+ call 1
+ call -2
+ call 0xa
+ call foo
+foo: call foo
+ call foo
+ call foo
--- /dev/null
+#as: --EB
+#source: exit.s
+#objdump: -dr
+#name: eBPF EXIT instruction, big endian
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: 95 00 00 00 00 00 00 00 exit
\ No newline at end of file
--- /dev/null
+#as: --EL
+#objdump: -dr
+#name: eBPF EXIT instruction
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: 95 00 00 00 00 00 00 00 exit
\ No newline at end of file
--- /dev/null
+ .text
+ exit
--- /dev/null
+#as: --EB
+#source: jump.s
+#objdump: -dr
+#name: eBPF JUMP instructions, big endian
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: 05 00 00 03 00 00 00 00 ja 3
+ 8: 0f 11 00 00 00 00 00 00 add %r1,%r1
+ 10: 15 30 00 01 00 00 00 03 jeq %r3,3,1
+ 18: 1d 34 00 00 00 00 00 00 jeq %r3,%r4,0
+ 20: 35 30 ff fd 00 00 00 03 jge %r3,3,-3
+ 28: 3d 34 ff fc 00 00 00 00 jge %r3,%r4,-4
+ 30: a5 30 00 01 00 00 00 03 jlt %r3,3,1
+ 38: ad 34 00 00 00 00 00 00 jlt %r3,%r4,0
+ 40: b5 30 00 01 00 00 00 03 jle %r3,3,1
+ 48: bd 34 00 00 00 00 00 00 jle %r3,%r4,0
+ 50: 45 30 00 01 00 00 00 03 jset %r3,3,1
+ 58: 4d 34 00 00 00 00 00 00 jset %r3,%r4,0
+ 60: 55 30 00 01 00 00 00 03 jne %r3,3,1
+ 68: 5d 34 00 00 00 00 00 00 jne %r3,%r4,0
+ 70: 65 30 00 01 00 00 00 03 jsgt %r3,3,1
+ 78: 6d 34 00 00 00 00 00 00 jsgt %r3,%r4,0
+ 80: 75 30 00 01 00 00 00 03 jsge %r3,3,1
+ 88: 7d 34 00 00 00 00 00 00 jsge %r3,%r4,0
+ 90: c5 30 00 01 00 00 00 03 jslt %r3,3,1
+ 98: cd 34 00 00 00 00 00 00 jslt %r3,%r4,0
+ a0: d5 30 00 01 00 00 00 03 jsle %r3,3,1
+ a8: dd 34 00 00 00 00 00 00 jsle %r3,%r4,0
--- /dev/null
+#as: --EL
+#objdump: -dr
+#name: eBPF JUMP instructions
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: 05 00 03 00 00 00 00 00 ja 3
+ 8: 0f 11 00 00 00 00 00 00 add %r1,%r1
+ 10: 15 03 01 00 03 00 00 00 jeq %r3,3,1
+ 18: 1d 43 00 00 00 00 00 00 jeq %r3,%r4,0
+ 20: 35 03 fd ff 03 00 00 00 jge %r3,3,-3
+ 28: 3d 43 fc ff 00 00 00 00 jge %r3,%r4,-4
+ 30: a5 03 01 00 03 00 00 00 jlt %r3,3,1
+ 38: ad 43 00 00 00 00 00 00 jlt %r3,%r4,0
+ 40: b5 03 01 00 03 00 00 00 jle %r3,3,1
+ 48: bd 43 00 00 00 00 00 00 jle %r3,%r4,0
+ 50: 45 03 01 00 03 00 00 00 jset %r3,3,1
+ 58: 4d 43 00 00 00 00 00 00 jset %r3,%r4,0
+ 60: 55 03 01 00 03 00 00 00 jne %r3,3,1
+ 68: 5d 43 00 00 00 00 00 00 jne %r3,%r4,0
+ 70: 65 03 01 00 03 00 00 00 jsgt %r3,3,1
+ 78: 6d 43 00 00 00 00 00 00 jsgt %r3,%r4,0
+ 80: 75 03 01 00 03 00 00 00 jsge %r3,3,1
+ 88: 7d 43 00 00 00 00 00 00 jsge %r3,%r4,0
+ 90: c5 03 01 00 03 00 00 00 jslt %r3,3,1
+ 98: cd 43 00 00 00 00 00 00 jslt %r3,%r4,0
+ a0: d5 03 01 00 03 00 00 00 jsle %r3,3,1
+ a8: dd 43 00 00 00 00 00 00 jsle %r3,%r4,0
\ No newline at end of file
--- /dev/null
+# Tests for the JUMP instructions
+ .text
+ ja 2f
+ add %r1,%r1
+1: jeq %r3,3,2f
+ jeq %r3,%r4,2f
+2: jge %r3,3,1b
+ jge %r3,%r4,1b
+1: jlt %r3,3,1f
+ jlt %r3,%r4,1f
+1: jle %r3,3,1f
+ jle %r3,%r4,1f
+1: jset %r3,3,1f
+ jset %r3,%r4,1f
+1: jne %r3,3,1f
+ jne %r3,%r4,1f
+1: jsgt %r3,3,1f
+ jsgt %r3,%r4,1f
+1: jsge %r3,3,1f
+ jsge %r3,%r4,1f
+1: jslt %r3,3,1f
+ jslt %r3,%r4,1f
+1: jsle %r3,3,1f
+ jsle %r3,%r4,1f
+1:
--- /dev/null
+#as: --EB
+#source: lddw.s
+#objdump: -dr
+#name: eBPF LDDW, big-endian
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: 18 30 00 00 00 00 00 01 lddw %r3,1
+ 8: 00 00 00 00 00 00 00 00
+ 10: 18 40 00 00 de ad be ef lddw %r4,0xdeadbeef
+ 18: 00 00 00 00 00 00 00 00
+ 20: 18 50 00 00 55 66 77 88 lddw %r5,0x1122334455667788
+ 28: 00 00 00 00 11 22 33 44
+ 30: 18 60 00 00 ff ff ff fe lddw %ctx,-2
+ 38: 00 00 00 00 ff ff ff ff
--- /dev/null
+#as: --EL
+#objdump: -dr
+#name: eBPF LDDW
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: 18 03 00 00 01 00 00 00 lddw %r3,1
+ 8: 00 00 00 00 00 00 00 00
+ 10: 18 04 00 00 ef be ad de lddw %r4,0xdeadbeef
+ 18: 00 00 00 00 00 00 00 00
+ 20: 18 05 00 00 88 77 66 55 lddw %r5,0x1122334455667788
+ 28: 00 00 00 00 44 33 22 11
+ 30: 18 06 00 00 fe ff ff ff lddw %ctx,-2
+ 38: 00 00 00 00 ff ff ff ff
--- /dev/null
+# Tests for the LDDW instruction
+ .text
+ lddw %r3, 1
+ lddw %r4, 0xdeadbeef
+ lddw %r5, 0x1122334455667788
+ lddw %r6, -2
--- /dev/null
+#as: --EB
+#source: mem.s
+#objdump: -dr
+#name: eBPF MEM instructions, modulus lddw, big endian
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: 20 23 00 00 00 00 be ef ldabsw %r2,%r3,0xbeef
+ 8: 28 45 00 00 00 00 be ef ldabsh %r4,%r5,0xbeef
+ 10: 30 67 00 00 00 00 be ef ldabsb %ctx,%r7,0xbeef
+ 18: 38 89 00 00 00 00 be ef ldabsdw %r8,%r9,0xbeef
+ 20: 40 23 00 00 00 00 be ef ldindw %r2,%r3,0xbeef
+ 28: 48 45 00 00 00 00 be ef ldindh %r4,%r5,0xbeef
+ 30: 50 67 00 00 00 00 be ef ldindb %ctx,%r7,0xbeef
+ 38: 58 89 00 00 00 00 be ef ldinddw %r8,%r9,0xbeef
+ 40: 61 21 7e ef 00 00 00 00 ldxw %r2,\[%r1\+0x7eef\]
+ 48: 69 21 7e ef 00 00 00 00 ldxh %r2,\[%r1\+0x7eef\]
+ 50: 71 21 7e ef 00 00 00 00 ldxb %r2,\[%r1\+0x7eef\]
+ 58: 79 21 ff fe 00 00 00 00 ldxdw %r2,\[%r1\+-2\]
+ 60: 63 12 7e ef 00 00 00 00 stxw \[%r1\+0x7eef\],%r2
+ 68: 6b 12 7e ef 00 00 00 00 stxh \[%r1\+0x7eef\],%r2
+ 70: 73 12 7e ef 00 00 00 00 stxb \[%r1\+0x7eef\],%r2
+ 78: 7b 12 ff fe 00 00 00 00 stxdw \[%r1\+-2\],%r2
+ 80: 72 10 7e ef 11 22 33 44 stb \[%r1\+0x7eef\],0x11223344
+ 88: 6a 10 7e ef 11 22 33 44 sth \[%r1\+0x7eef\],0x11223344
+ 90: 62 10 7e ef 11 22 33 44 stw \[%r1\+0x7eef\],0x11223344
+ 98: 7a 10 ff fe 11 22 33 44 stdw \[%r1\+-2\],0x11223344
\ No newline at end of file
--- /dev/null
+#as: --EL
+#objdump: -dr
+#name: eBPF MEM instructions, modulus lddw
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: 20 32 00 00 ef be 00 00 ldabsw %r2,%r3,0xbeef
+ 8: 28 54 00 00 ef be 00 00 ldabsh %r4,%r5,0xbeef
+ 10: 30 76 00 00 ef be 00 00 ldabsb %ctx,%r7,0xbeef
+ 18: 38 98 00 00 ef be 00 00 ldabsdw %r8,%r9,0xbeef
+ 20: 40 32 00 00 ef be 00 00 ldindw %r2,%r3,0xbeef
+ 28: 48 54 00 00 ef be 00 00 ldindh %r4,%r5,0xbeef
+ 30: 50 76 00 00 ef be 00 00 ldindb %ctx,%r7,0xbeef
+ 38: 58 98 00 00 ef be 00 00 ldinddw %r8,%r9,0xbeef
+ 40: 61 12 ef 7e 00 00 00 00 ldxw %r2,\[%r1\+0x7eef\]
+ 48: 69 12 ef 7e 00 00 00 00 ldxh %r2,\[%r1\+0x7eef\]
+ 50: 71 12 ef 7e 00 00 00 00 ldxb %r2,\[%r1\+0x7eef\]
+ 58: 79 12 fe ff 00 00 00 00 ldxdw %r2,\[%r1\+-2\]
+ 60: 63 21 ef 7e 00 00 00 00 stxw \[%r1\+0x7eef\],%r2
+ 68: 6b 21 ef 7e 00 00 00 00 stxh \[%r1\+0x7eef\],%r2
+ 70: 73 21 ef 7e 00 00 00 00 stxb \[%r1\+0x7eef\],%r2
+ 78: 7b 21 fe ff 00 00 00 00 stxdw \[%r1\+-2\],%r2
+ 80: 72 01 ef 7e 44 33 22 11 stb \[%r1\+0x7eef\],0x11223344
+ 88: 6a 01 ef 7e 44 33 22 11 sth \[%r1\+0x7eef\],0x11223344
+ 90: 62 01 ef 7e 44 33 22 11 stw \[%r1\+0x7eef\],0x11223344
+ 98: 7a 01 fe ff 44 33 22 11 stdw \[%r1\+-2\],0x11223344
--- /dev/null
+# eBPF tests for MEM instructions, modulus lddw.
+
+ .text
+
+ ldabsw %r2, %r3, 0xbeef
+ ldabsh %r4, %r5, 0xbeef
+ ldabsb %r6, %r7, 0xbeef
+ ldabsdw %r8, %r9, 0xbeef
+ ldindw %r2, %r3, 0xbeef
+ ldindh %r4, %r5, 0xbeef
+ ldindb %r6, %r7, 0xbeef
+ ldinddw %r8, %r9, 0xbeef
+ ldxw %r2, [%r1+0x7eef]
+ ldxh %r2, [%r1+0x7eef]
+ ldxb %r2, [%r1+0x7eef]
+ ldxdw %r2, [%r1+-2]
+ stxw [%r1+0x7eef], %r2
+ stxh [%r1+0x7eef], %r2
+ stxb [%r1+0x7eef], %r2
+ stxdw [%r1+-2], %r2
+ stb [%r1+0x7eef], 0x11223344
+ sth [%r1+0x7eef], 0x11223344
+ stw [%r1+0x7eef], 0x11223344
+ stdw [%r1+-2], 0x11223344
projects / binutils-gdb.git / commitdiff