Finish implementation of r5900 instructions.

diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog
index 2f04fb5a1e18a7e7e9de79f5a3b5355519df3d0d..8d2c5e085ff68d39aa8990ae3d284a0507b84b57 100644 (file)
--- a/sim/mips/ChangeLog
+++ b/sim/mips/ChangeLog
@@ -1,3 +1,24 @@
+Wed Feb 25 18:56:22 1998  Andrew Cagney  <cagney@b1.cygnus.com>
+
+       * mips.igen (CxC1): Add tracing.
+
+start-sanitize-r5900
+Wed Feb 25 13:59:03 1998  Andrew Cagney  <cagney@b1.cygnus.com>
+
+       * r5900.igen (StoreFP): Delete.
+       (r59fp_store, r59fp_overflow, r59fp_op1, r59fp_op2, r59fp_op3):
+       New functions.
+       (rsqrt.s, sqrt.s): Implement.
+       (r59cond): New function.
+       (C.COND.S): Call r59cond in assembler line.
+       (cvt.w.s, cvt.s.w): Implement.
+       
+       * mips.igen (rsqrt.fmt, sqrt.fmt, cvt.*.*): Remove from r5900
+       instruction set.
+
+       * sim-main.h: Define an enum of r5900 FCSR bit fields.
+       
+end-sanitize-r5900
 start-sanitize-r5900
 Tue Feb 24 14:44:18 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 

diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen
index 50a8248fc6a2df36d4062600fecc5510ab13c75d..839ae7a12e207458acc4e9ddb2645b2bd8bc2c48 100644 (file)
--- a/sim/mips/mips.igen
+++ b/sim/mips/mips.igen
@@ -3718,19 +3718,38 @@
 {
   if (X)
     {
+      /* control to */
+      TRACE_ALU_INPUT1 (GPR[RT]);
       if (FS == 0)
-       FCR0 = VL4_8(GPR[RT]);
+       {
+         FCR0 = VL4_8(GPR[RT]);
+         TRACE_ALU_RESULT (FCR0);
+       }
       else if (FS == 31)
-       FCR31 = VL4_8(GPR[RT]);
+       {
+         FCR31 = VL4_8(GPR[RT]);
+         SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
+         TRACE_ALU_RESULT (FCR31);
+       }
+      else
+       {
+         TRACE_ALU_RESULT0 ();
+       }
       /* else NOP */
-      SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
     }
   else
     { /* control from */
       if (FS == 0)
-       GPR[RT] = SIGNEXTEND (FCR0, 32);
+       {
+         TRACE_ALU_INPUT1 (FCR0);
+         GPR[RT] = SIGNEXTEND (FCR0, 32);
+       }
       else if (FS == 31)
-       GPR[RT] = SIGNEXTEND (FCR31, 32);
+       {
+         TRACE_ALU_INPUT1 (FCR31);
+         GPR[RT] = SIGNEXTEND (FCR31, 32);
+       }
+      TRACE_ALU_RESULT (GPR[RT]);
       /* else NOP */
     }
 }
@@ -3746,9 +3765,6 @@
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
 // start-sanitize-tx19
 *tx19:
@@ -3775,9 +3791,6 @@
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
 // start-sanitize-tx19
 *tx19:
@@ -3806,9 +3819,6 @@
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
 // start-sanitize-tx19
 *tx19:
@@ -3834,9 +3844,6 @@
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
 // start-sanitize-tx19
 *tx19:
@@ -4711,9 +4718,6 @@
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
 // start-sanitize-tx19
 *tx19:

diff --git a/sim/mips/sim-main.h b/sim/mips/sim-main.h
index 457811a034bb8225e74dbd1edbccfa1a483f3e32..5dd7071d25dd1fa1c285930d98742fb81f23f140 100644 (file)
--- a/sim/mips/sim-main.h
+++ b/sim/mips/sim-main.h
@@ -188,6 +188,22 @@ convert (SD, CPU, cia, rm, op, from, to)
 
 /* start-sanitize-r5900 */
 
+/* Figure 10-5 FPU Control/Status Register.
+   Note: some of these bits are different to what is found in a
+   standard MIPS manual. */
+enum {
+  R5900_FCSR_C = BIT (23), /* OK */
+  R5900_FCSR_I = BIT (17),
+  R5900_FCSR_D = BIT (16),
+  R5900_FCSR_O = BIT (15),
+  R5900_FCSR_U = BIT (14),
+  R5900_FCSR_CAUSE = MASK (16,14),
+  R5900_FCSR_SI = BIT (6),
+  R5900_FCSR_SD = BIT (5),
+  R5900_FCSR_SO = BIT (4),
+  R5900_FCSR_SU = BIT (3),
+};
+
 typedef struct _sim_r5900_cpu {
 
   /* The R5900 has 32 x 128bit general purpose registers.