real.c (encode_ieee_extended): Initialize whole array.

	* real.c (encode_ieee_extended): Initialize whole array.
	* reg-stack.c (move_for_stack_reg0: Use always XFmode.
	* i386-modes.def: Change definitions of TFmode and XFmode.
	* i386.c (classify_argument): Rename TFmodes to XFmodes; add new TFmode code.
	(construct_container): Allow constructing of TFmode integer containers.
	(ix86_return_in_memory):  XFmode is not returned in memory.
	(init_ext_80387_constants): Always use XFmode.
	(print_operand): Likewise.
	(ix86_prepare_fp_compare_regs): Likewise.
	(split_to_parts): Deal with TFmode.
	(split_long_move): Simplify.
	(ix86_init_mmx_sse_builtins): Add __float80, __float128.
	(ix86_memory_move_cost): Do not confuse TFmode.
	* i386.h (LONG_DOUBLE_TYPE_SIZE): Set to 96.
	(IS_STACK_MODE): TFmode is not stack mode.
	(HARD_REGNO_NREGS, CLASS_MAX_NREGS): Deal nicely with XFmode.
	(VALID_SSE_REG_MODE): Allow TFmode.
	(VALID_FP_MODE_P): Disallow TFmode.
	(VALID_INT_MODE_P): Allow TFmode in 64bit mode.
	* i386.md (TFmode patterns): Kill.
	(movtf, motf_rex64): New patterns.

From-SVN: r73099

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d32301ce4bdd37a06470ed92d33a3739ff58bb90..63738b63ffd1b29248cf55068e124518c0f18d44 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,27 @@
+2003-10-30  Jan Hubicka  <jh@suse.cz>
+
+       * real.c (encode_ieee_extended): Initialize whole array.
+       * reg-stack.c (move_for_stack_reg0: Use always XFmode.
+       * i386-modes.def: Change definitions of TFmode and XFmode.
+       * i386.c (classify_argument): Rename TFmodes to XFmodes; add new TFmode code.
+       (construct_container): Allow constructing of TFmode integer containers.
+       (ix86_return_in_memory):  XFmode is not returned in memory.
+       (init_ext_80387_constants): Always use XFmode.
+       (print_operand): Likewise.
+       (ix86_prepare_fp_compare_regs): Likewise.
+       (split_to_parts): Deal with TFmode.
+       (split_long_move): Simplify.
+       (ix86_init_mmx_sse_builtins): Add __float80, __float128.
+       (ix86_memory_move_cost): Do not confuse TFmode.
+       * i386.h (LONG_DOUBLE_TYPE_SIZE): Set to 96.
+       (IS_STACK_MODE): TFmode is not stack mode.
+       (HARD_REGNO_NREGS, CLASS_MAX_NREGS): Deal nicely with XFmode.
+       (VALID_SSE_REG_MODE): Allow TFmode.
+       (VALID_FP_MODE_P): Disallow TFmode.
+       (VALID_INT_MODE_P): Allow TFmode in 64bit mode.
+       * i386.md (TFmode patterns): Kill.
+       (movtf, motf_rex64): New patterns.
+
 2003-10-30  Richard Sandiford  <rsandifo@redhat.com>
 
        * config/mips/mips.md (adddi3): Fix typo in mips16 stack pointer code.

diff --git a/gcc/config/i386/i386-modes.def b/gcc/config/i386/i386-modes.def
index ddfc5cfcf521c22c434d44f4b196c1fc3405dc95..9f52f7f0b1b7eef8a47cbc6e1093936943fadd4f 100644 (file)
--- a/gcc/config/i386/i386-modes.def
+++ b/gcc/config/i386/i386-modes.def
@@ -18,11 +18,18 @@ along with GCC; see the file COPYING.  If not, write to
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
-/* By default our XFmode is the 80-bit extended format.  If we use
-   TFmode instead, it's also the 80-bit format, but with padding. */
+/* x86_64 ABI specifies both XF and TF modes.
+   XFmode is __float80 is IEEE extended; TFmode is __float128
+   is IEEE quad.
+
+   IEEE extended is 128 bits wide, except in ILP32 mode, but we
+   have to say it's 12 bytes so that the bitsize and wider_mode
+   tables are correctly set up.  We correct its size below.  */
 
 FLOAT_MODE (XF, 12, ieee_extended_intel_96_format);
-FLOAT_MODE (TF, 16, ieee_extended_intel_128_format);
+ADJUST_BYTESIZE  (XF, TARGET_128BIT_LONG_DOUBLE ? 16 : 12);
+ADJUST_ALIGNMENT (XF, TARGET_128BIT_LONG_DOUBLE ? 16 : 4);
+FLOAT_MODE (TF, 16, ieee_quad_format);
 
 /* Add any extra modes needed to represent the condition code.
 

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index a5d27fcbde725c8d92c7afbd83364425591c6e38..a42f1746317a1531e6d8a6538a3188c0d569520e 100644 (file)
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -1374,6 +1374,7 @@ override_options (void)
   if (TARGET_SSE2)
     target_flags |= MASK_SSE;
 
+      target_flags |= (MASK_128BIT_LONG_DOUBLE);
   if (TARGET_64BIT)
     {
       if (TARGET_ALIGN_DOUBLE)
@@ -2182,6 +2183,7 @@ classify_argument (enum machine_mode mode, tree type,
       return 1;
     case CDImode:
     case TImode:
+    case TCmode:
       classes[0] = classes[1] = X86_64_INTEGER_CLASS;
       return 2;
     case CTImode:
@@ -2197,11 +2199,15 @@ classify_argument (enum machine_mode mode, tree type,
     case DFmode:
       classes[0] = X86_64_SSEDF_CLASS;
       return 1;
-    case TFmode:
+    case XFmode:
       classes[0] = X86_64_X87_CLASS;
       classes[1] = X86_64_X87UP_CLASS;
       return 2;
-    case TCmode:
+    case TFmode:
+      classes[0] = X86_64_INTEGER_CLASS;
+      classes[1] = X86_64_INTEGER_CLASS;
+      return 2;
+    case XCmode:
       classes[0] = X86_64_X87_CLASS;
       classes[1] = X86_64_X87UP_CLASS;
       classes[2] = X86_64_X87_CLASS;
@@ -2338,16 +2344,16 @@ construct_container (enum machine_mode mode, tree type, int in_return,
     return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
   if (n == 2
       && class[0] == X86_64_X87_CLASS && class[1] == X86_64_X87UP_CLASS)
-    return gen_rtx_REG (TFmode, FIRST_STACK_REG);
+    return gen_rtx_REG (XFmode, FIRST_STACK_REG);
   if (n == 2 && class[0] == X86_64_INTEGER_CLASS
       && class[1] == X86_64_INTEGER_CLASS
-      && (mode == CDImode || mode == TImode)
+      && (mode == CDImode || mode == TImode || mode == TFmode)
       && intreg[0] + 1 == intreg[1])
     return gen_rtx_REG (mode, intreg[0]);
   if (n == 4
       && class[0] == X86_64_X87_CLASS && class[1] == X86_64_X87UP_CLASS
       && class[2] == X86_64_X87_CLASS && class[3] == X86_64_X87UP_CLASS)
-    return gen_rtx_REG (TCmode, FIRST_STACK_REG);
+    return gen_rtx_REG (XCmode, FIRST_STACK_REG);
 
   /* Otherwise figure out the entries of the PARALLEL.  */
   for (i = 0; i < n; i++)
@@ -2779,8 +2785,9 @@ ix86_return_in_memory (tree type)
        }
     }
 
-  if (mode == TFmode)
+  if (mode == TFmode || mode == XFmode)
     return 0;
+
   if (size > 12)
     return 1;
   return 0;
@@ -2795,20 +2802,35 @@ ix86_libcall_value (enum machine_mode mode)
     {
       switch (mode)
        {
-         case SFmode:
-         case SCmode:
-         case DFmode:
-         case DCmode:
-           return gen_rtx_REG (mode, FIRST_SSE_REG);
-         case TFmode:
-         case TCmode:
-           return gen_rtx_REG (mode, FIRST_FLOAT_REG);
-         default:
-           return gen_rtx_REG (mode, 0);
+       case SFmode:
+       case SCmode:
+       case DFmode:
+       case DCmode:
+         return gen_rtx_REG (mode, FIRST_SSE_REG);
+       case XFmode:
+       case XCmode:
+         return gen_rtx_REG (mode, FIRST_FLOAT_REG);
+       case TFmode:
+         {
+           rtx ret = gen_rtx_PARALLEL (mode, rtvec_alloc (2));
+           XVECEXP (ret, 0, 0) = gen_rtx_EXPR_LIST
+              (VOIDmode,
+               gen_rtx_REG (DImode, x86_64_int_parameter_registers [0]),
+                            const0_rtx);
+           XVECEXP (ret, 0, 1) = gen_rtx_EXPR_LIST
+              (VOIDmode,
+               gen_rtx_REG (DImode, x86_64_int_parameter_registers [1]),
+                            GEN_INT (64));
+           return ret;
+         }
+       case TCmode:
+         return NULL;
+       default:
+         return gen_rtx_REG (mode, 0);
        }
     }
   else
-   return gen_rtx_REG (mode, ix86_value_regno (mode));
+    return gen_rtx_REG (mode, ix86_value_regno (mode));
 }
 
 /* Given a mode, return the register to use for a return value.  */
@@ -4257,8 +4279,7 @@ init_ext_80387_constants (void)
       real_from_string (&ext_80387_constants_table[i], cst[i]);
       /* Ensure each constant is rounded to XFmode precision.  */
       real_convert (&ext_80387_constants_table[i],
-                   TARGET_128BIT_LONG_DOUBLE ? TFmode : XFmode,
-                   &ext_80387_constants_table[i]);
+                   XFmode, &ext_80387_constants_table[i]);
     }
 
   ext_80387_constants_init = 1;
@@ -4280,7 +4301,7 @@ standard_80387_constant_p (rtx x)
 
   /* For XFmode constants, try to find a special 80387 instruction on
      those CPUs that benefit from them.  */
-  if ((GET_MODE (x) == XFmode || GET_MODE (x) == TFmode)
+  if (GET_MODE (x) == XFmode
       && x86_ext_80387_constants & TUNEMASK)
     {
       REAL_VALUE_TYPE r;
@@ -4351,7 +4372,7 @@ standard_80387_constant_rtx (int idx)
     }
 
   return CONST_DOUBLE_FROM_REAL_VALUE (ext_80387_constants_table[i],
-                                      TARGET_128BIT_LONG_DOUBLE ? TFmode : XFmode);
+                                      XFmode);
 }
 
 /* Return 1 if X is FP constant we can load to SSE register w/o using memory.
@@ -7450,7 +7471,7 @@ print_operand (FILE *file, rtx x, int code)
     }
 
   else if (GET_CODE (x) == CONST_DOUBLE
-          && (GET_MODE (x) == XFmode || GET_MODE (x) == TFmode))
+          && GET_MODE (x) == XFmode)
     {
       char dstr[30];
 
@@ -8690,7 +8711,6 @@ ix86_prepare_fp_compare_args (enum rtx_code code, rtx *pop0, rtx *pop1)
   if (!is_sse
       && (fpcmp_mode == CCFPUmode
          || op_mode == XFmode
-         || op_mode == TFmode
          || ix86_use_fcomi_compare (code)))
     {
       op0 = force_reg (op_mode, op0);
@@ -9165,7 +9185,6 @@ ix86_expand_branch (enum rtx_code code, rtx label)
     case SFmode:
     case DFmode:
     case XFmode:
-    case TFmode:
       {
        rtvec vec;
        int use_fcomi;
@@ -10356,7 +10375,7 @@ ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode)
   int size;
 
   if (!TARGET_64BIT)
-    size = mode == TFmode ? 3 : (GET_MODE_SIZE (mode) / 4);
+    size = mode==XFmode ? 3 : GET_MODE_SIZE (mode) / 4;
   else
     size = (GET_MODE_SIZE (mode) + 4) / 8;
 
@@ -10416,7 +10435,6 @@ ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode)
              switch (mode)
                {
                case XFmode:
-               case TFmode:
                  REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
                  parts[2] = gen_int_mode (l[2], SImode);
                  break;
@@ -10439,18 +10457,19 @@ ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode)
        split_ti (&operand, 1, &parts[0], &parts[1]);
       if (mode == XFmode || mode == TFmode)
        {
+         enum machine_mode upper_mode = mode==XFmode ? SImode : DImode;
          if (REG_P (operand))
            {
              if (!reload_completed)
                abort ();
              parts[0] = gen_rtx_REG (DImode, REGNO (operand) + 0);
-             parts[1] = gen_rtx_REG (SImode, REGNO (operand) + 1);
+             parts[1] = gen_rtx_REG (upper_mode, REGNO (operand) + 1);
            }
          else if (offsettable_memref_p (operand))
            {
              operand = adjust_address (operand, DImode, 0);
              parts[0] = operand;
-             parts[1] = adjust_address (operand, SImode, 8);
+             parts[1] = adjust_address (operand, upper_mode, 8);
            }
          else if (GET_CODE (operand) == CONST_DOUBLE)
            {
@@ -10468,7 +10487,16 @@ ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode)
                       DImode);
              else
                parts[0] = immed_double_const (l[0], l[1], DImode);
-             parts[1] = gen_int_mode (l[2], SImode);
+             if (upper_mode == SImode)
+               parts[1] = gen_int_mode (l[2], SImode);
+             else if (HOST_BITS_PER_WIDE_INT >= 64)
+               parts[1]
+                 = gen_int_mode
+                     ((l[2] & (((HOST_WIDE_INT) 2 << 31) - 1))
+                      + ((((HOST_WIDE_INT) l[3]) << 31) << 1),
+                      DImode);
+             else
+               parts[1] = immed_double_const (l[2], l[3], DImode);
            }
          else
            abort ();
@@ -10589,12 +10617,8 @@ ix86_split_long_move (rtx operands[])
        {
          if (nparts == 3)
            {
-             /* We use only first 12 bytes of TFmode value, but for pushing we
-                are required to adjust stack as if we were pushing real 16byte
-                value.  */
-             if (mode == TFmode && !TARGET_64BIT)
-               emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
-                                      GEN_INT (-4)));
+             if (TARGET_128BIT_LONG_DOUBLE && mode == XFmode)
+                emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, GEN_INT (-4)));
              emit_move_insn (part[0][2], part[1][2]);
            }
        }
@@ -13305,6 +13329,27 @@ ix86_init_mmx_sse_builtins (void)
   tree v2di_ftype_v2di
     = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE);
 
+  tree float80_type;
+  tree float128_type;
+
+  /* The __float80 type.  */
+  if (TYPE_MODE (long_double_type_node) == XFmode)
+    (*lang_hooks.types.register_builtin_type) (long_double_type_node,
+                                              "__float80");
+  else
+    {
+      /* The __float80 type.  */
+      float80_type = make_node (REAL_TYPE);
+      TYPE_PRECISION (float80_type) = 96;
+      layout_type (float80_type);
+      (*lang_hooks.types.register_builtin_type) (float80_type, "__float80");
+    }
+
+  float128_type = make_node (REAL_TYPE);
+  TYPE_PRECISION (float128_type) = 128;
+  layout_type (float128_type);
+  (*lang_hooks.types.register_builtin_type) (float128_type, "__float128");
+
   /* Add all builtins that are more or less simple operations on two
      operands.  */
   for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
@@ -14745,7 +14790,6 @@ ix86_memory_move_cost (enum machine_mode mode, enum reg_class class, int in)
            index = 1;
            break;
          case XFmode:
-         case TFmode:
            index = 2;
            break;
          default:

diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index d6133e9402aa31c680445e67774717aa4ee56e36..24a234172efa4918be8bc1a776aa510ddea34f7f 100644 (file)
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -721,16 +721,7 @@ extern int x86_prefetch_sse;
 \f
 /* target machine storage layout */
 
-/* Define for XFmode or TFmode extended real floating point support.
-   The XFmode is specified by i386 ABI, while TFmode may be faster
-   due to alignment and simplifications in the address calculations.  */
-#define LONG_DOUBLE_TYPE_SIZE (TARGET_128BIT_LONG_DOUBLE ? 128 : 96)
-#define MAX_LONG_DOUBLE_TYPE_SIZE 128
-#ifdef __x86_64__
-#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
-#else
-#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 96
-#endif
+#define LONG_DOUBLE_TYPE_SIZE 96
 
 /* Set the value of FLT_EVAL_METHOD in float.h.  When using only the
    FPU, assume that the fpcw is set to extended precision; when using
@@ -900,8 +891,7 @@ extern int x86_prefetch_sse;
 
 #define STACK_REGS
 #define IS_STACK_MODE(MODE)                                    \
-  ((MODE) == DFmode || (MODE) == SFmode || (MODE) == XFmode    \
-   || (MODE) == TFmode)
+  ((MODE) == DFmode || (MODE) == SFmode || (MODE) == XFmode)   \
 
 /* Number of actual hardware registers.
    The hardware registers are assigned numbers for the compiler
@@ -1049,9 +1039,9 @@ do {                                                                      \
 #define HARD_REGNO_NREGS(REGNO, MODE)   \
   (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO)    \
    ? (COMPLEX_MODE_P (MODE) ? 2 : 1)                                   \
-   : ((MODE) == TFmode                                                 \
+   : ((MODE) == XFmode                                                 \
       ? (TARGET_64BIT ? 2 : 3)                                         \
-      : (MODE) == TCmode                                               \
+      : (MODE) == XCmode                                               \
       ? (TARGET_64BIT ? 4 : 6)                                         \
       : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
 
@@ -1061,7 +1051,7 @@ do {                                                                      \
 
 #define VALID_SSE_REG_MODE(MODE)                                       \
     ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode      \
-     || (MODE) == SFmode                                               \
+     || (MODE) == SFmode || (MODE) == TFmode                           \
      /* Always accept SSE2 modes so that xmmintrin.h compiles.  */     \
      || VALID_SSE2_REG_MODE (MODE)                                     \
      || (TARGET_SSE2 && ((MODE) == DFmode || VALID_MMX_REG_MODE (MODE))))
@@ -1079,21 +1069,20 @@ do {                                                                    \
      : VALID_MMX_REG_MODE_3DNOW (MODE) && TARGET_3DNOW ? 1 : 0)
 
 #define VALID_FP_MODE_P(MODE)                                          \
-    ((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode          \
-     || (!TARGET_64BIT && (MODE) == XFmode)                            \
-     || (MODE) == SCmode || (MODE) == DCmode || (MODE) == TCmode       \
-     || (!TARGET_64BIT && (MODE) == XCmode))
+    ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode          \
+     || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode)      \
 
 #define VALID_INT_MODE_P(MODE)                                         \
     ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode          \
      || (MODE) == DImode                                               \
      || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode    \
      || (MODE) == CDImode                                              \
-     || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode)))
+     || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode                \
+         || (MODE) == TFmode || (MODE) == TCmode)))
 
 /* Return true for modes passed in SSE registers.  */
 #define SSE_REG_MODE_P(MODE) \
- ((MODE) == TImode || (MODE) == V16QImode                              \
+ ((MODE) == TImode || (MODE) == V16QImode || (MODE) == TFmode          \
    || (MODE) == V8HImode || (MODE) == V2DFmode || (MODE) == V2DImode   \
    || (MODE) == V4SFmode || (MODE) == V4SImode)
 
@@ -1568,15 +1557,12 @@ enum reg_class
 /* Return the maximum number of consecutive registers
    needed to represent mode MODE in a register of class CLASS.  */
 /* On the 80386, this is the size of MODE in words,
-   except in the FP regs, where a single reg is always enough.
-   The TFmodes are really just 80bit values, so we use only 3 registers
-   to hold them, instead of 4, as the size would suggest.
- */
+   except in the FP regs, where a single reg is always enough.  */
 #define CLASS_MAX_NREGS(CLASS, MODE)                                   \
  (!MAYBE_INTEGER_CLASS_P (CLASS)                                       \
   ? (COMPLEX_MODE_P (MODE) ? 2 : 1)                                    \
-  : ((GET_MODE_SIZE ((MODE) == TFmode ? XFmode : (MODE))               \
-     + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
+  : (((((MODE) == XFmode ? 12 : GET_MODE_SIZE (MODE)))                 \
+      + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
 
 /* A C expression whose value is nonzero if pseudos that have been
    assigned to registers of class CLASS would likely be spilled

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index f9acc04ec7b56c23817bf530c34890e0d97abb77..4ef4124c904b851caf7b837e0d7d0fe121a03d37 100644 (file)
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -716,17 +716,6 @@
   [(set (reg:CC 17)
        (compare:CC (match_operand:XF 0 "cmp_fp_expander_operand" "")
                    (match_operand:XF 1 "cmp_fp_expander_operand" "")))]
-  "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
-{
-  ix86_compare_op0 = operands[0];
-  ix86_compare_op1 = operands[1];
-  DONE;
-})
-
-(define_expand "cmptf"
-  [(set (reg:CC 17)
-       (compare:CC (match_operand:TF 0 "cmp_fp_expander_operand" "")
-                   (match_operand:TF 1 "cmp_fp_expander_operand" "")))]
   "TARGET_80387"
 {
   ix86_compare_op0 = operands[0];
@@ -850,16 +839,6 @@
        (compare:CCFP
          (match_operand:XF 0 "register_operand" "f")
          (match_operand:XF 1 "register_operand" "f")))]
-  "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
-  "* return output_fp_compare (insn, operands, 0, 0);"
-  [(set_attr "type" "fcmp")
-   (set_attr "mode" "XF")])
-
-(define_insn "*cmpfp_2_tf"
-  [(set (reg:CCFP 18)
-       (compare:CCFP
-         (match_operand:TF 0 "register_operand" "f")
-         (match_operand:TF 1 "register_operand" "f")))]
   "TARGET_80387"
   "* return output_fp_compare (insn, operands, 0, 0);"
   [(set_attr "type" "fcmp")
@@ -872,18 +851,6 @@
             (match_operand:XF 1 "register_operand" "f")
             (match_operand:XF 2 "register_operand" "f"))]
          UNSPEC_FNSTSW))]
-  "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
-  "* return output_fp_compare (insn, operands, 2, 0);"
-  [(set_attr "type" "multi")
-   (set_attr "mode" "XF")])
-
-(define_insn "*cmpfp_2_tf_1"
-  [(set (match_operand:HI 0 "register_operand" "=a")
-       (unspec:HI
-         [(compare:CCFP
-            (match_operand:TF 1 "register_operand" "f")
-            (match_operand:TF 2 "register_operand" "f"))]
-         UNSPEC_FNSTSW))]
   "TARGET_80387"
   "* return output_fp_compare (insn, operands, 2, 0);"
   [(set_attr "type" "multi")
@@ -2744,14 +2711,8 @@
 (define_expand "movxf"
   [(set (match_operand:XF 0 "nonimmediate_operand" "")
        (match_operand:XF 1 "general_operand" ""))]
-  "!TARGET_128BIT_LONG_DOUBLE"
-  "ix86_expand_move (XFmode, operands); DONE;")
-
-(define_expand "movtf"
-  [(set (match_operand:TF 0 "nonimmediate_operand" "")
-       (match_operand:TF 1 "general_operand" ""))]
   ""
-  "ix86_expand_move (TFmode, operands); DONE;")
+  "ix86_expand_move (XFmode, operands); DONE;")
 
 ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
 ;; Size of pushdf using integer instructions is 3+3*memory operand size
@@ -2763,17 +2724,6 @@
 (define_insn "*pushxf_nointeger"
   [(set (match_operand:XF 0 "push_operand" "=X,X,X")
        (match_operand:XF 1 "general_no_elim_operand" "f,Fo,*r"))]
-  "!TARGET_128BIT_LONG_DOUBLE && optimize_size"
-{
-  /* This insn should be already splitted before reg-stack.  */
-  abort ();
-}
-  [(set_attr "type" "multi")
-   (set_attr "mode" "XF,SI,SI")])
-
-(define_insn "*pushtf_nointeger"
-  [(set (match_operand:TF 0 "push_operand" "=<,<,<")
-       (match_operand:TF 1 "general_no_elim_operand" "f,Fo,*r"))]
   "optimize_size"
 {
   /* This insn should be already splitted before reg-stack.  */
@@ -2785,17 +2735,6 @@
 (define_insn "*pushxf_integer"
   [(set (match_operand:XF 0 "push_operand" "=<,<")
        (match_operand:XF 1 "general_no_elim_operand" "f#r,ro#f"))]
-  "!TARGET_128BIT_LONG_DOUBLE && !optimize_size"
-{
-  /* This insn should be already splitted before reg-stack.  */
-  abort ();
-}
-  [(set_attr "type" "multi")
-   (set_attr "mode" "XF,SI")])
-
-(define_insn "*pushtf_integer"
-  [(set (match_operand:TF 0 "push_operand" "=<,<")
-       (match_operand:TF 1 "general_no_elim_operand" "f#r,rFo#f"))]
   "!optimize_size"
 {
   /* This insn should be already splitted before reg-stack.  */
@@ -2809,7 +2748,6 @@
        (match_operand 1 "general_operand" ""))]
   "reload_completed
    && (GET_MODE (operands[0]) == XFmode
-       || GET_MODE (operands[0]) == TFmode
        || GET_MODE (operands[0]) == DFmode)
    && !ANY_FP_REG_P (operands[1])"
   [(const_int 0)]
@@ -2818,30 +2756,24 @@
 (define_split
   [(set (match_operand:XF 0 "push_operand" "")
        (match_operand:XF 1 "any_fp_register_operand" ""))]
-  "!TARGET_128BIT_LONG_DOUBLE"
-  [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
-   (set (mem:XF (reg:SI 7)) (match_dup 1))])
-
-(define_split
-  [(set (match_operand:TF 0 "push_operand" "")
-       (match_operand:TF 1 "any_fp_register_operand" ""))]
   "!TARGET_64BIT"
-  [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
-   (set (mem:TF (reg:SI 7)) (match_dup 1))])
+  [(set (reg:SI 7) (plus:SI (reg:SI 7) (match_dup 2)))
+   (set (mem:XF (reg:SI 7)) (match_dup 1))]
+  "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
 
 (define_split
-  [(set (match_operand:TF 0 "push_operand" "")
-       (match_operand:TF 1 "any_fp_register_operand" ""))]
+  [(set (match_operand:XF 0 "push_operand" "")
+       (match_operand:XF 1 "any_fp_register_operand" ""))]
   "TARGET_64BIT"
-  [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
-   (set (mem:TF (reg:DI 7)) (match_dup 1))])
+  [(set (reg:DI 7) (plus:DI (reg:DI 7) (match_dup 2)))
+   (set (mem:XF (reg:DI 7)) (match_dup 1))]
+  "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
 
 ;; Do not use integer registers when optimizing for size
 (define_insn "*movxf_nointeger"
   [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,*r,o")
        (match_operand:XF 1 "general_operand" "fm,f,G,*roF,F*r"))]
-  "!TARGET_128BIT_LONG_DOUBLE
-   && optimize_size
+  "optimize_size
    && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
    && (reload_in_progress || reload_completed
        || GET_CODE (operands[1]) != CONST_DOUBLE
@@ -2882,56 +2814,10 @@
   [(set_attr "type" "fmov,fmov,fmov,multi,multi")
    (set_attr "mode" "XF,XF,XF,SI,SI")])
 
-(define_insn "*movtf_nointeger"
-  [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m,f,*r,o")
-       (match_operand:TF 1 "general_operand" "fm,f,G,*roF,F*r"))]
-  "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
-   && optimize_size
-   && (reload_in_progress || reload_completed
-       || GET_CODE (operands[1]) != CONST_DOUBLE
-       || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
-       || memory_operand (operands[0], TFmode))" 
-{
-  switch (which_alternative)
-    {
-    case 0:
-      if (REG_P (operands[1])
-          && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
-       {
-         if (REGNO (operands[0]) == FIRST_STACK_REG
-             && TARGET_USE_FFREEP)
-           return "ffreep\t%y0";
-          return "fstp\t%y0";
-       }
-      else if (STACK_TOP_P (operands[0]))
-        return "fld%z1\t%y1";
-      else
-        return "fst\t%y0";
-
-    case 1:
-      /* There is no non-popping store to memory for XFmode.  So if
-        we need one, follow the store with a load.  */
-      if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
-        return "fstp%z0\t%y0\;fld%z0\t%y0";
-      else
-        return "fstp%z0\t%y0";
-
-    case 2:
-      return standard_80387_constant_opcode (operands[1]);
-
-    case 3: case 4:
-      return "#";
-    }
-  abort();
-}
-  [(set_attr "type" "fmov,fmov,fmov,multi,multi")
-   (set_attr "mode" "XF,XF,XF,SI,SI")])
-
 (define_insn "*movxf_integer"
   [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o")
        (match_operand:XF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))]
-  "!TARGET_128BIT_LONG_DOUBLE
-   && !optimize_size
+  "!optimize_size
    && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
    && (reload_in_progress || reload_completed
        || GET_CODE (operands[1]) != CONST_DOUBLE
@@ -2972,57 +2858,12 @@
   [(set_attr "type" "fmov,fmov,fmov,multi,multi")
    (set_attr "mode" "XF,XF,XF,SI,SI")])
 
-(define_insn "*movtf_integer"
-  [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o")
-       (match_operand:TF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))]
-  "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
-   && !optimize_size
-   && (reload_in_progress || reload_completed
-       || GET_CODE (operands[1]) != CONST_DOUBLE
-       || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
-       || memory_operand (operands[0], TFmode))" 
-{
-  switch (which_alternative)
-    {
-    case 0:
-      if (REG_P (operands[1])
-          && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
-       {
-         if (REGNO (operands[0]) == FIRST_STACK_REG
-             && TARGET_USE_FFREEP)
-           return "ffreep\t%y0";
-          return "fstp\t%y0";
-       }
-      else if (STACK_TOP_P (operands[0]))
-        return "fld%z1\t%y1";
-      else
-        return "fst\t%y0";
-
-    case 1:
-      /* There is no non-popping store to memory for XFmode.  So if
-        we need one, follow the store with a load.  */
-      if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
-        return "fstp%z0\t%y0\;fld%z0\t%y0";
-      else
-        return "fstp%z0\t%y0";
-
-    case 2:
-      return standard_80387_constant_opcode (operands[1]);
-
-    case 3: case 4:
-      return "#";
-    }
-  abort();
-}
-  [(set_attr "type" "fmov,fmov,fmov,multi,multi")
-   (set_attr "mode" "XF,XF,XF,SI,SI")])
-
 (define_split
   [(set (match_operand 0 "nonimmediate_operand" "")
        (match_operand 1 "general_operand" ""))]
   "reload_completed
    && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
-   && (GET_MODE (operands[0]) == XFmode || GET_MODE (operands[0]) == TFmode)
+   && GET_MODE (operands[0]) == XFmode
    && ! (ANY_FP_REG_P (operands[0]) || 
         (GET_CODE (operands[0]) == SUBREG
          && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
@@ -3037,7 +2878,7 @@
        (match_operand 1 "memory_operand" ""))]
   "reload_completed
    && GET_CODE (operands[1]) == MEM
-   && (GET_MODE (operands[0]) == XFmode || GET_MODE (operands[0]) == TFmode
+   && (GET_MODE (operands[0]) == XFmode
        || GET_MODE (operands[0]) == SFmode || GET_MODE (operands[0]) == DFmode)
    && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
    && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))
@@ -3067,21 +2908,6 @@
 }
   [(set_attr "type" "fxch")
    (set_attr "mode" "XF")])
-
-(define_insn "swaptf"
-  [(set (match_operand:TF 0 "register_operand" "+f")
-       (match_operand:TF 1 "register_operand" "+f"))
-   (set (match_dup 1)
-       (match_dup 0))]
-  ""
-{
-  if (STACK_TOP_P (operands[0]))
-    return "fxch\t%1";
-  else
-    return "fxch\t%0";
-}
-  [(set_attr "type" "fxch")
-   (set_attr "mode" "XF")])
 \f
 ;; Zero extension instructions
 
@@ -3632,62 +3458,34 @@
 (define_split
   [(set (match_operand:XF 0 "push_operand" "")
        (float_extend:XF (match_operand:SF 1 "fp_register_operand" "")))]
-  "!TARGET_128BIT_LONG_DOUBLE"
-  [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
-   (set (mem:XF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
-
-(define_insn "*dummy_extendsftf2"
-  [(set (match_operand:TF 0 "push_operand" "=<")
-       (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "f")))]
-  "0"
-  "#")
-
-(define_split
-  [(set (match_operand:TF 0 "push_operand" "")
-       (float_extend:TF (match_operand:SF 1 "fp_register_operand" "")))]
-  "!TARGET_64BIT"
-  [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
-   (set (mem:TF (reg:SI 7)) (float_extend:TF (match_dup 1)))])
+  ""
+  [(set (reg:SI 7) (plus:SI (reg:SI 7) (match_dup 2)))
+   (set (mem:XF (reg:SI 7)) (float_extend:XF (match_dup 1)))]
+  "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
 
 (define_split
-  [(set (match_operand:TF 0 "push_operand" "")
-       (float_extend:TF (match_operand:SF 1 "fp_register_operand" "")))]
+  [(set (match_operand:XF 0 "push_operand" "")
+       (float_extend:XF (match_operand:SF 1 "fp_register_operand" "")))]
   "TARGET_64BIT"
-  [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
-   (set (mem:DF (reg:DI 7)) (float_extend:TF (match_dup 1)))])
-
-(define_insn "*dummy_extenddfxf2"
-  [(set (match_operand:XF 0 "push_operand" "=<")
-       (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "f")))]
-  "0"
-  "#")
+  [(set (reg:DI 7) (plus:DI (reg:DI 7) (match_dup 2)))
+   (set (mem:DF (reg:DI 7)) (float_extend:XF (match_dup 1)))]
+  "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
 
 (define_split
   [(set (match_operand:XF 0 "push_operand" "")
        (float_extend:XF (match_operand:DF 1 "fp_register_operand" "")))]
-  "!TARGET_128BIT_LONG_DOUBLE"
-  [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
-   (set (mem:DF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
-
-(define_insn "*dummy_extenddftf2"
-  [(set (match_operand:TF 0 "push_operand" "=<")
-       (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "f")))]
-  "0"
-  "#")
-
-(define_split
-  [(set (match_operand:TF 0 "push_operand" "")
-       (float_extend:TF (match_operand:DF 1 "fp_register_operand" "")))]
-  "!TARGET_64BIT"
-  [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
-   (set (mem:TF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
+  ""
+  [(set (reg:SI 7) (plus:SI (reg:SI 7) (match_dup 2)))
+   (set (mem:DF (reg:SI 7)) (float_extend:XF (match_dup 1)))]
+  "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
 
 (define_split
-  [(set (match_operand:TF 0 "push_operand" "")
-       (float_extend:TF (match_operand:DF 1 "fp_register_operand" "")))]
+  [(set (match_operand:XF 0 "push_operand" "")
+       (float_extend:XF (match_operand:DF 1 "fp_register_operand" "")))]
   "TARGET_64BIT"
-  [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
-   (set (mem:TF (reg:DI 7)) (float_extend:TF (match_dup 1)))])
+  [(set (reg:DI 7) (plus:DI (reg:DI 7) (match_dup 2)))
+   (set (mem:XF (reg:DI 7)) (float_extend:XF (match_dup 1)))]
+  "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
 
 (define_expand "extendsfdf2"
   [(set (match_operand:DF 0 "nonimmediate_operand" "")
@@ -3747,7 +3545,7 @@
 (define_expand "extendsfxf2"
   [(set (match_operand:XF 0 "nonimmediate_operand" "")
         (float_extend:XF (match_operand:SF 1 "general_operand" "")))]
-  "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
+  "TARGET_80387"
 {
   /* ??? Needed for compress_float_constant since all fp constants
      are LEGITIMATE_CONSTANT_P.  */
@@ -3760,51 +3558,6 @@
 (define_insn "*extendsfxf2_1"
   [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
         (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
-  "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387
-   && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
-{
-  switch (which_alternative)
-    {
-    case 0:
-      if (REG_P (operands[1])
-          && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
-        return "fstp\t%y0";
-      else if (STACK_TOP_P (operands[0]))
-        return "fld%z1\t%y1";
-      else
-        return "fst\t%y0";
-
-    case 1:
-      /* There is no non-popping store to memory for XFmode.  So if
-        we need one, follow the store with a load.  */
-      if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
-        return "fstp%z0\t%y0\n\tfld%z0\t%y0";
-      else
-        return "fstp%z0\t%y0";
-
-    default:
-      abort ();
-    }
-}
-  [(set_attr "type" "fmov")
-   (set_attr "mode" "SF,XF")])
-
-(define_expand "extendsftf2"
-  [(set (match_operand:TF 0 "nonimmediate_operand" "")
-        (float_extend:TF (match_operand:SF 1 "general_operand" "")))]
-  "TARGET_80387"
-{
-  /* ??? Needed for compress_float_constant since all fp constants
-     are LEGITIMATE_CONSTANT_P.  */
-  if (GET_CODE (operands[1]) == CONST_DOUBLE)
-    operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
-  if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
-    operands[1] = force_reg (SFmode, operands[1]);
-})
-
-(define_insn "*extendsftf2_1"
-  [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m")
-        (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
   "TARGET_80387
    && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
 {
@@ -3837,7 +3590,7 @@
 (define_expand "extenddfxf2"
   [(set (match_operand:XF 0 "nonimmediate_operand" "")
         (float_extend:XF (match_operand:DF 1 "general_operand" "")))]
-  "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
+  "TARGET_80387"
 {
   /* ??? Needed for compress_float_constant since all fp constants
      are LEGITIMATE_CONSTANT_P.  */
@@ -3850,51 +3603,6 @@
 (define_insn "*extenddfxf2_1"
   [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
         (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
-  "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387
-   && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
-{
-  switch (which_alternative)
-    {
-    case 0:
-      if (REG_P (operands[1])
-          && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
-        return "fstp\t%y0";
-      else if (STACK_TOP_P (operands[0]))
-        return "fld%z1\t%y1";
-      else
-        return "fst\t%y0";
-
-    case 1:
-      /* There is no non-popping store to memory for XFmode.  So if
-        we need one, follow the store with a load.  */
-      if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
-        return "fstp%z0\t%y0\n\tfld%z0\t%y0";
-      else
-        return "fstp%z0\t%y0";
-
-    default:
-      abort ();
-    }
-}
-  [(set_attr "type" "fmov")
-   (set_attr "mode" "DF,XF")])
-
-(define_expand "extenddftf2"
-  [(set (match_operand:TF 0 "nonimmediate_operand" "")
-        (float_extend:TF (match_operand:DF 1 "general_operand" "")))]
-  "TARGET_80387"
-{
-  /* ??? Needed for compress_float_constant since all fp constants
-     are LEGITIMATE_CONSTANT_P.  */
-  if (GET_CODE (operands[1]) == CONST_DOUBLE)
-    operands[1] = validize_mem (force_const_mem (DFmode, operands[1]));
-  if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
-    operands[1] = force_reg (DFmode, operands[1]);
-})
-
-(define_insn "*extenddftf2_1"
-  [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m")
-        (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
   "TARGET_80387
    && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
 {
@@ -4169,7 +3877,7 @@
                   (float_truncate:SF
                    (match_operand:XF 1 "register_operand" "")))
              (clobber (match_dup 2))])]
-  "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
+  "TARGET_80387"
   "operands[2] = assign_386_stack_local (SFmode, 0);")
 
 (define_insn "*truncxfsf2_1"
@@ -4177,7 +3885,7 @@
        (float_truncate:SF
         (match_operand:XF 1 "register_operand" "f,f,f,f")))
    (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
-  "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
+  "TARGET_80387"
 {
   switch (which_alternative)
     {
@@ -4197,7 +3905,7 @@
   [(set (match_operand:SF 0 "memory_operand" "=m")
        (float_truncate:SF
         (match_operand:XF 1 "register_operand" "f")))]
-  "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
+  "TARGET_80387"
 {
   if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
     return "fstp%z0\t%y0";
@@ -4226,75 +3934,12 @@
    (set (match_dup 0) (match_dup 2))]
   "")
 
-(define_expand "trunctfsf2"
-  [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
-                  (float_truncate:SF
-                   (match_operand:TF 1 "register_operand" "")))
-             (clobber (match_dup 2))])]
-  "TARGET_80387"
-  "operands[2] = assign_386_stack_local (SFmode, 0);")
-
-(define_insn "*trunctfsf2_1"
-  [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
-       (float_truncate:SF
-        (match_operand:TF 1 "register_operand" "f,f,f,f")))
-   (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
-  "TARGET_80387"
-{
-  switch (which_alternative)
-    {
-    case 0:
-      if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
-       return "fstp%z0\t%y0";
-      else
-       return "fst%z0\t%y0";
-    default:
-      abort();
-    }
-}
-  [(set_attr "type" "fmov,multi,multi,multi")
-   (set_attr "mode" "SF")])
-
-(define_insn "*trunctfsf2_2"
-  [(set (match_operand:SF 0 "memory_operand" "=m")
-       (float_truncate:SF
-        (match_operand:TF 1 "register_operand" "f")))]
-  "TARGET_80387"
-{
-  if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
-    return "fstp%z0\t%y0";
-  else
-    return "fst%z0\t%y0";
-}
-  [(set_attr "type" "fmov")
-   (set_attr "mode" "SF")])
-
-(define_split
-  [(set (match_operand:SF 0 "memory_operand" "")
-       (float_truncate:SF
-        (match_operand:TF 1 "register_operand" "")))
-   (clobber (match_operand:SF 2 "memory_operand" ""))]
-  "TARGET_80387"
-  [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
-  "")
-
-(define_split
-  [(set (match_operand:SF 0 "register_operand" "")
-       (float_truncate:SF
-        (match_operand:TF 1 "register_operand" "")))
-   (clobber (match_operand:SF 2 "memory_operand" ""))]
-  "TARGET_80387 && reload_completed"
-  [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
-   (set (match_dup 0) (match_dup 2))]
-  "")
-
-
 (define_expand "truncxfdf2"
   [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
                   (float_truncate:DF
                    (match_operand:XF 1 "register_operand" "")))
              (clobber (match_dup 2))])]
-  "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
+  "TARGET_80387"
   "operands[2] = assign_386_stack_local (DFmode, 0);")
 
 (define_insn "*truncxfdf2_1"
@@ -4302,7 +3947,7 @@
        (float_truncate:DF
         (match_operand:XF 1 "register_operand" "f,f,f,f")))
    (clobber (match_operand:DF 2 "memory_operand" "=X,m,m,m"))]
-  "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
+  "TARGET_80387"
 {
   switch (which_alternative)
     {
@@ -4323,7 +3968,7 @@
   [(set (match_operand:DF 0 "memory_operand" "=m")
        (float_truncate:DF
          (match_operand:XF 1 "register_operand" "f")))]
-  "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
+  "TARGET_80387"
 {
   if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
     return "fstp%z0\t%y0";
@@ -4352,69 +3997,6 @@
    (set (match_dup 0) (match_dup 2))]
   "")
 
-(define_expand "trunctfdf2"
-  [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
-                  (float_truncate:DF
-                   (match_operand:TF 1 "register_operand" "")))
-             (clobber (match_dup 2))])]
-  "TARGET_80387"
-  "operands[2] = assign_386_stack_local (DFmode, 0);")
-
-(define_insn "*trunctfdf2_1"
-  [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f#rY,?r#fY,?Y#rf")
-       (float_truncate:DF
-        (match_operand:TF 1 "register_operand" "f,f,f,f")))
-   (clobber (match_operand:DF 2 "memory_operand" "=X,m,m,m"))]
-  "TARGET_80387"
-{
-  switch (which_alternative)
-    {
-    case 0:
-      if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
-       return "fstp%z0\t%y0";
-      else
-       return "fst%z0\t%y0";
-    default:
-      abort();
-    }
-  abort ();
-}
-  [(set_attr "type" "fmov,multi,multi,multi")
-   (set_attr "mode" "DF")])
-
-       (define_insn "*trunctfdf2_2"
-  [(set (match_operand:DF 0 "memory_operand" "=m")
-       (float_truncate:DF
-         (match_operand:TF 1 "register_operand" "f")))]
-  "TARGET_80387"
-{
-  if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
-    return "fstp%z0\t%y0";
-  else
-    return "fst%z0\t%y0";
-}
-  [(set_attr "type" "fmov")
-   (set_attr "mode" "DF")])
-
-(define_split
-  [(set (match_operand:DF 0 "memory_operand" "")
-       (float_truncate:DF
-        (match_operand:TF 1 "register_operand" "")))
-   (clobber (match_operand:DF 2 "memory_operand" ""))]
-  "TARGET_80387"
-  [(set (match_dup 0) (float_truncate:DF (match_dup 1)))]
-  "")
-
-(define_split
-  [(set (match_operand:DF 0 "register_operand" "")
-       (float_truncate:DF
-        (match_operand:TF 1 "register_operand" "")))
-   (clobber (match_operand:DF 2 "memory_operand" ""))]
-  "TARGET_80387 && reload_completed"
-  [(set (match_dup 2) (float_truncate:DF (match_dup 1)))
-   (set (match_dup 0) (match_dup 2))]
-  "")
-
 \f
 ;; %%% Break up all these bad boys.
 
@@ -4423,12 +4005,6 @@
 (define_expand "fix_truncxfdi2"
   [(set (match_operand:DI 0 "nonimmediate_operand" "")
         (fix:DI (match_operand:XF 1 "register_operand" "")))]
-  "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
-  "")
-
-(define_expand "fix_trunctfdi2"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "")
-       (fix:DI (match_operand:TF 1 "register_operand" "")))]
   "TARGET_80387"
   "")
 
@@ -4590,12 +4166,6 @@
 (define_expand "fix_truncxfsi2"
   [(set (match_operand:SI 0 "nonimmediate_operand" "")
        (fix:SI (match_operand:XF 1 "register_operand" "")))]
-  "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
-  "")
-
-(define_expand "fix_trunctfsi2"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "")
-       (fix:SI (match_operand:TF 1 "register_operand" "")))]
   "TARGET_80387"
   "")
 
@@ -4751,12 +4321,6 @@
 (define_expand "fix_truncxfhi2"
   [(set (match_operand:HI 0 "nonimmediate_operand" "")
         (fix:HI (match_operand:XF 1 "register_operand" "")))]
-  "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
-  "")
-
-(define_expand "fix_trunctfhi2"
-  [(set (match_operand:HI 0 "nonimmediate_operand" "")
-       (fix:HI (match_operand:TF 1 "register_operand" "")))]
   "TARGET_80387"
   "")
 
@@ -5103,17 +4667,6 @@
 (define_insn "floathixf2"
   [(set (match_operand:XF 0 "register_operand" "=f,f")
        (float:XF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
-  "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
-  "@
-   fild%z1\t%1
-   #"
-  [(set_attr "type" "fmov,multi")
-   (set_attr "mode" "XF")
-   (set_attr "fp_int_src" "true")])
-
-(define_insn "floathitf2"
-  [(set (match_operand:TF 0 "register_operand" "=f,f")
-       (float:TF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
   "TARGET_80387"
   "@
    fild%z1\t%1
@@ -5125,17 +4678,6 @@
 (define_insn "floatsixf2"
   [(set (match_operand:XF 0 "register_operand" "=f,f")
        (float:XF (match_operand:SI 1 "nonimmediate_operand" "m,r")))]
-  "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
-  "@
-   fild%z1\t%1
-   #"
-  [(set_attr "type" "fmov,multi")
-   (set_attr "mode" "XF")
-   (set_attr "fp_int_src" "true")])
-
-(define_insn "floatsitf2"
-  [(set (match_operand:TF 0 "register_operand" "=f,f")
-       (float:TF (match_operand:SI 1 "nonimmediate_operand" "m,r")))]
   "TARGET_80387"
   "@
    fild%z1\t%1
@@ -5147,17 +4689,6 @@
 (define_insn "floatdixf2"
   [(set (match_operand:XF 0 "register_operand" "=f,f")
        (float:XF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
-  "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
-  "@
-   fild%z1\t%1
-   #"
-  [(set_attr "type" "fmov,multi")
-   (set_attr "mode" "XF")
-   (set_attr "fp_int_src" "true")])
-
-(define_insn "floatditf2"
-  [(set (match_operand:TF 0 "register_operand" "=f,f")
-       (float:TF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
   "TARGET_80387"
   "@
    fild%z1\t%1
@@ -6858,13 +6389,6 @@
   [(set (match_operand:XF 0 "register_operand" "")
        (plus:XF (match_operand:XF 1 "register_operand" "")
                 (match_operand:XF 2 "register_operand" "")))]
-  "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
-  "")
-
-(define_expand "addtf3"
-  [(set (match_operand:TF 0 "register_operand" "")
-       (plus:TF (match_operand:TF 1 "register_operand" "")
-                (match_operand:TF 2 "register_operand" "")))]
   "TARGET_80387"
   "")
 
@@ -7211,13 +6735,6 @@
   [(set (match_operand:XF 0 "register_operand" "")
        (minus:XF (match_operand:XF 1 "register_operand" "")
                  (match_operand:XF 2 "register_operand" "")))]
-  "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
-  "")
-
-(define_expand "subtf3"
-  [(set (match_operand:TF 0 "register_operand" "")
-       (minus:TF (match_operand:TF 1 "register_operand" "")
-                 (match_operand:TF 2 "register_operand" "")))]
   "TARGET_80387"
   "")
 
@@ -7729,13 +7246,6 @@
   [(set (match_operand:XF 0 "register_operand" "")
        (mult:XF (match_operand:XF 1 "register_operand" "")
                 (match_operand:XF 2 "register_operand" "")))]
-  "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
-  "")
-
-(define_expand "multf3"
-  [(set (match_operand:TF 0 "register_operand" "")
-       (mult:TF (match_operand:TF 1 "register_operand" "")
-                (match_operand:TF 2 "register_operand" "")))]
   "TARGET_80387"
   "")
 
@@ -7783,13 +7293,6 @@
   [(set (match_operand:XF 0 "register_operand" "")
        (div:XF (match_operand:XF 1 "register_operand" "")
                (match_operand:XF 2 "register_operand" "")))]
-  "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
-  "")
-
-(define_expand "divtf3"
-  [(set (match_operand:TF 0 "register_operand" "")
-       (div:TF (match_operand:TF 1 "register_operand" "")
-               (match_operand:TF 2 "register_operand" "")))]
   "TARGET_80387"
   "")
 
@@ -10018,8 +9521,7 @@
 {
   int size = GET_MODE_SIZE (GET_MODE (operands[1]));
 
-  /* XFmode's size is 12, TFmode 16, but only 10 bytes are used.  */
-  if (size >= 12)
+  if (GET_MODE (operands[1]) == XFmode)
     size = 10;
   operands[0] = adjust_address (operands[0], QImode, size - 1);
   operands[1] = gen_int_mode (0x80, QImode);
@@ -10196,15 +9698,8 @@
   [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
                   (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
              (clobber (reg:CC 17))])]
-  "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
-  "ix86_expand_unary_operator (NEG, XFmode, operands); DONE;")
-
-(define_expand "negtf2"
-  [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
-                  (neg:TF (match_operand:TF 1 "nonimmediate_operand" "")))
-             (clobber (reg:CC 17))])]
   "TARGET_80387"
-  "ix86_expand_unary_operator (NEG, TFmode, operands); DONE;")
+  "ix86_expand_unary_operator (NEG, XFmode, operands); DONE;")
 
 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
@@ -10213,7 +9708,7 @@
   [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
        (neg:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
    (clobber (reg:CC 17))]
-  "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387
+  "TARGET_80387
    && ix86_unary_operator_ok (NEG, XFmode, operands)"
   "#")
 
@@ -10237,36 +9732,6 @@
    operands[0] = gen_rtx_REG (SImode,
                              true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
 
-;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
-;; because of secondary memory needed to reload from class FLOAT_INT_REGS
-;; to itself.
-(define_insn "*negtf2_if"
-  [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,rm#f")
-       (neg:TF (match_operand:TF 1 "nonimmediate_operand" "0,0")))
-   (clobber (reg:CC 17))]
-  "TARGET_80387 && ix86_unary_operator_ok (NEG, TFmode, operands)"
-  "#")
-
-(define_split
-  [(set (match_operand:TF 0 "fp_register_operand" "")
-       (neg:TF (match_operand:TF 1 "register_operand" "")))
-   (clobber (reg:CC 17))]
-  "TARGET_80387 && reload_completed"
-  [(set (match_dup 0)
-       (neg:TF (match_dup 1)))]
-  "")
-
-(define_split
-  [(set (match_operand:TF 0 "register_and_not_fp_reg_operand" "")
-       (neg:TF (match_operand:TF 1 "register_operand" "")))
-   (clobber (reg:CC 17))]
-  "TARGET_80387 && reload_completed"
-  [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
-             (clobber (reg:CC 17))])]
-  "operands[1] = GEN_INT (0x8000);
-   operands[0] = gen_rtx_REG (SImode,
-                             true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
-
 ;; Conditionalize these after reload. If they matches before reload, we 
 ;; lose the clobber and ability to use integer instructions.
 
@@ -10301,7 +9766,7 @@
 (define_insn "*negxf2_1"
   [(set (match_operand:XF 0 "register_operand" "=f")
        (neg:XF (match_operand:XF 1 "register_operand" "0")))]
-  "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387 && reload_completed"
+  "TARGET_80387 && reload_completed"
   "fchs"
   [(set_attr "type" "fsgn")
    (set_attr "mode" "XF")
@@ -10311,7 +9776,7 @@
   [(set (match_operand:XF 0 "register_operand" "=f")
        (neg:XF (float_extend:XF
                  (match_operand:DF 1 "register_operand" "0"))))]
-  "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
+  "TARGET_80387"
   "fchs"
   [(set_attr "type" "fsgn")
    (set_attr "mode" "XF")
@@ -10321,35 +9786,6 @@
   [(set (match_operand:XF 0 "register_operand" "=f")
        (neg:XF (float_extend:XF
                  (match_operand:SF 1 "register_operand" "0"))))]
-  "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
-  "fchs"
-  [(set_attr "type" "fsgn")
-   (set_attr "mode" "XF")
-   (set_attr "ppro_uops" "few")])
-
-(define_insn "*negtf2_1"
-  [(set (match_operand:TF 0 "register_operand" "=f")
-       (neg:TF (match_operand:TF 1 "register_operand" "0")))]
-  "TARGET_80387 && reload_completed"
-  "fchs"
-  [(set_attr "type" "fsgn")
-   (set_attr "mode" "XF")
-   (set_attr "ppro_uops" "few")])
-
-(define_insn "*negextenddftf2"
-  [(set (match_operand:TF 0 "register_operand" "=f")
-       (neg:TF (float_extend:TF
-                 (match_operand:DF 1 "register_operand" "0"))))]
-  "TARGET_80387"
-  "fchs"
-  [(set_attr "type" "fsgn")
-   (set_attr "mode" "XF")
-   (set_attr "ppro_uops" "few")])
-
-(define_insn "*negextendsftf2"
-  [(set (match_operand:TF 0 "register_operand" "=f")
-       (neg:TF (float_extend:TF
-                 (match_operand:SF 1 "register_operand" "0"))))]
   "TARGET_80387"
   "fchs"
   [(set_attr "type" "fsgn")
@@ -10491,8 +9927,7 @@
 {
   int size = GET_MODE_SIZE (GET_MODE (operands[1]));
 
-  /* XFmode's size is 12, TFmode 16, but only 10 bytes are used.  */
-  if (size >= 12)
+  if (GET_MODE (operands[1]) == XFmode)
     size = 10;
   operands[0] = adjust_address (operands[0], QImode, size - 1);
   operands[1] = gen_int_mode (~0x80, QImode);
@@ -10658,15 +10093,8 @@
   [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
                   (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
              (clobber (reg:CC 17))])]
-  "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
-  "ix86_expand_unary_operator (ABS, XFmode, operands); DONE;")
-
-(define_expand "abstf2"
-  [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
-                  (neg:TF (match_operand:TF 1 "nonimmediate_operand" "")))
-             (clobber (reg:CC 17))])]
   "TARGET_80387"
-  "ix86_expand_unary_operator (ABS, TFmode, operands); DONE;")
+  "ix86_expand_unary_operator (ABS, XFmode, operands); DONE;")
 
 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
@@ -10675,7 +10103,7 @@
   [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
        (abs:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
    (clobber (reg:CC 17))]
-  "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387
+  "TARGET_80387
    && ix86_unary_operator_ok (ABS, XFmode, operands)"
   "#")
 
@@ -10699,33 +10127,6 @@
    operands[0] = gen_rtx_REG (SImode,
                              true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
 
-(define_insn "*abstf2_if"
-  [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,rm#f")
-       (abs:TF (match_operand:TF 1 "nonimmediate_operand" "0,0")))
-   (clobber (reg:CC 17))]
-  "TARGET_80387 && ix86_unary_operator_ok (ABS, TFmode, operands)"
-  "#")
-
-(define_split
-  [(set (match_operand:TF 0 "fp_register_operand" "")
-       (abs:TF (match_operand:TF 1 "register_operand" "")))
-   (clobber (reg:CC 17))]
-  "TARGET_80387 && reload_completed"
-  [(set (match_dup 0)
-       (abs:TF (match_dup 1)))]
-  "")
-
-(define_split
-  [(set (match_operand:TF 0 "register_and_not_any_fp_reg_operand" "")
-       (abs:TF (match_operand:TF 1 "register_operand" "")))
-   (clobber (reg:CC 17))]
-  "TARGET_80387 && reload_completed"
-  [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
-             (clobber (reg:CC 17))])]
-  "operands[1] = GEN_INT (~0x8000);
-   operands[0] = gen_rtx_REG (SImode,
-                             true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
-
 (define_insn "*abssf2_1"
   [(set (match_operand:SF 0 "register_operand" "=f")
        (abs:SF (match_operand:SF 1 "register_operand" "0")))]
@@ -10754,7 +10155,7 @@
 (define_insn "*absxf2_1"
   [(set (match_operand:XF 0 "register_operand" "=f")
        (abs:XF (match_operand:XF 1 "register_operand" "0")))]
-  "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387 && reload_completed"
+  "TARGET_80387 && reload_completed"
   "fabs"
   [(set_attr "type" "fsgn")
    (set_attr "mode" "DF")])
@@ -10763,7 +10164,7 @@
   [(set (match_operand:XF 0 "register_operand" "=f")
        (abs:XF (float_extend:XF
          (match_operand:DF 1 "register_operand" "0"))))]
-  "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
+  "TARGET_80387"
   "fabs"
   [(set_attr "type" "fsgn")
    (set_attr "mode" "XF")])
@@ -10772,32 +10173,6 @@
   [(set (match_operand:XF 0 "register_operand" "=f")
        (abs:XF (float_extend:XF
          (match_operand:SF 1 "register_operand" "0"))))]
-  "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
-  "fabs"
-  [(set_attr "type" "fsgn")
-   (set_attr "mode" "XF")])
-
-(define_insn "*abstf2_1"
-  [(set (match_operand:TF 0 "register_operand" "=f")
-       (abs:TF (match_operand:TF 1 "register_operand" "0")))]
-  "TARGET_80387 && reload_completed"
-  "fabs"
-  [(set_attr "type" "fsgn")
-   (set_attr "mode" "DF")])
-
-(define_insn "*absextenddftf2"
-  [(set (match_operand:TF 0 "register_operand" "=f")
-       (abs:TF (float_extend:TF
-         (match_operand:DF 1 "register_operand" "0"))))]
-  "TARGET_80387"
-  "fabs"
-  [(set_attr "type" "fsgn")
-   (set_attr "mode" "XF")])
-
-(define_insn "*absextendsftf2"
-  [(set (match_operand:TF 0 "register_operand" "=f")
-       (abs:TF (float_extend:TF
-         (match_operand:SF 1 "register_operand" "0"))))]
   "TARGET_80387"
   "fabs"
   [(set_attr "type" "fsgn")
@@ -14841,7 +14216,7 @@
        (match_operator:XF 3 "binary_fp_operator"
                        [(match_operand:XF 1 "register_operand" "%0")
                         (match_operand:XF 2 "register_operand" "f")]))]
-  "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387
+  "TARGET_80387
    && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
   "* return output_387_binary_op (insn, operands);"
   [(set (attr "type") 
@@ -14850,19 +14225,6 @@
            (const_string "fop")))
    (set_attr "mode" "XF")])
 
-(define_insn "*fop_tf_comm"
-  [(set (match_operand:TF 0 "register_operand" "=f")
-       (match_operator:TF 3 "binary_fp_operator"
-                       [(match_operand:TF 1 "register_operand" "%0")
-                        (match_operand:TF 2 "register_operand" "f")]))]
-  "TARGET_80387 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
-  "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (if_then_else (match_operand:TF 3 "mult_operator" "") 
-           (const_string "fmul")
-           (const_string "fop")))
-   (set_attr "mode" "XF")])
-
 (define_insn "*fop_sf_1_nosse"
   [(set (match_operand:SF 0 "register_operand" "=f,f")
        (match_operator:SF 3 "binary_fp_operator"
@@ -15117,7 +14479,7 @@
        (match_operator:XF 3 "binary_fp_operator"
                        [(match_operand:XF 1 "register_operand" "0,f")
                         (match_operand:XF 2 "register_operand" "f,0")]))]
-  "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387
+  "TARGET_80387
    && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
   "* return output_387_binary_op (insn, operands);"
   [(set (attr "type") 
@@ -15129,52 +14491,17 @@
               (const_string "fop")))
    (set_attr "mode" "XF")])
 
-(define_insn "*fop_tf_1"
-  [(set (match_operand:TF 0 "register_operand" "=f,f")
-       (match_operator:TF 3 "binary_fp_operator"
-                       [(match_operand:TF 1 "register_operand" "0,f")
-                        (match_operand:TF 2 "register_operand" "f,0")]))]
-  "TARGET_80387
-   && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
-  "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (cond [(match_operand:TF 3 "mult_operator" "") 
-                 (const_string "fmul")
-               (match_operand:TF 3 "div_operator" "") 
-                 (const_string "fdiv")
-              ]
-              (const_string "fop")))
-   (set_attr "mode" "XF")])
-
 (define_insn "*fop_xf_2"
   [(set (match_operand:XF 0 "register_operand" "=f,f")
        (match_operator:XF 3 "binary_fp_operator"
           [(float:XF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
            (match_operand:XF 2 "register_operand" "0,0")]))]
-  "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387 && TARGET_USE_FIOP"
-  "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (cond [(match_operand:XF 3 "mult_operator" "") 
-                 (const_string "fmul")
-               (match_operand:XF 3 "div_operator" "") 
-                 (const_string "fdiv")
-              ]
-              (const_string "fop")))
-   (set_attr "fp_int_src" "true")
-   (set_attr "mode" "SI")
-   (set_attr "ppro_uops" "many")])
-
-(define_insn "*fop_tf_2"
-  [(set (match_operand:TF 0 "register_operand" "=f,f")
-       (match_operator:TF 3 "binary_fp_operator"
-          [(float:TF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
-           (match_operand:TF 2 "register_operand" "0,0")]))]
   "TARGET_80387 && TARGET_USE_FIOP"
   "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
   [(set (attr "type") 
-        (cond [(match_operand:TF 3 "mult_operator" "") 
+        (cond [(match_operand:XF 3 "mult_operator" "") 
                  (const_string "fmul")
-               (match_operand:TF 3 "div_operator" "") 
+               (match_operand:XF 3 "div_operator" "") 
                  (const_string "fdiv")
               ]
               (const_string "fop")))
@@ -15187,7 +14514,7 @@
        (match_operator:XF 3 "binary_fp_operator"
          [(match_operand:XF 1 "register_operand" "0,0")
           (float:XF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
-  "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387 && TARGET_USE_FIOP"
+  "TARGET_80387 && TARGET_USE_FIOP"
   "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
   [(set (attr "type") 
         (cond [(match_operand:XF 3 "mult_operator" "") 
@@ -15200,30 +14527,12 @@
    (set_attr "mode" "SI")
    (set_attr "ppro_uops" "many")])
 
-(define_insn "*fop_tf_3"
-  [(set (match_operand:TF 0 "register_operand" "=f,f")
-       (match_operator:TF 3 "binary_fp_operator"
-         [(match_operand:TF 1 "register_operand" "0,0")
-          (float:TF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
-  "TARGET_80387 && TARGET_USE_FIOP"
-  "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (cond [(match_operand:TF 3 "mult_operator" "") 
-                 (const_string "fmul")
-               (match_operand:TF 3 "div_operator" "") 
-                 (const_string "fdiv")
-              ]
-              (const_string "fop")))
-   (set_attr "fp_int_src" "true")
-   (set_attr "mode" "SI")
-   (set_attr "ppro_uops" "many")])
-
 (define_insn "*fop_xf_4"
   [(set (match_operand:XF 0 "register_operand" "=f,f")
        (match_operator:XF 3 "binary_fp_operator"
           [(float_extend:XF (match_operand 1 "nonimmediate_operand" "fm,0"))
            (match_operand:XF 2 "register_operand" "0,f")]))]
-  "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
+  "TARGET_80387"
   "* return output_387_binary_op (insn, operands);"
   [(set (attr "type") 
         (cond [(match_operand:XF 3 "mult_operator" "") 
@@ -15234,29 +14543,13 @@
               (const_string "fop")))
    (set_attr "mode" "SF")])
 
-(define_insn "*fop_tf_4"
-  [(set (match_operand:TF 0 "register_operand" "=f,f")
-       (match_operator:TF 3 "binary_fp_operator"
-          [(float_extend:TF (match_operand 1 "nonimmediate_operand" "fm,0"))
-           (match_operand:TF 2 "register_operand" "0,f")]))]
-  "TARGET_80387"
-  "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (cond [(match_operand:TF 3 "mult_operator" "") 
-                 (const_string "fmul")
-               (match_operand:TF 3 "div_operator" "") 
-                 (const_string "fdiv")
-              ]
-              (const_string "fop")))
-   (set_attr "mode" "SF")])
-
 (define_insn "*fop_xf_5"
   [(set (match_operand:XF 0 "register_operand" "=f,f")
        (match_operator:XF 3 "binary_fp_operator"
          [(match_operand:XF 1 "register_operand" "0,f")
           (float_extend:XF
            (match_operand 2 "nonimmediate_operand" "fm,0"))]))]
-  "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
+  "TARGET_80387"
   "* return output_387_binary_op (insn, operands);"
   [(set (attr "type") 
         (cond [(match_operand:XF 3 "mult_operator" "") 
@@ -15267,23 +14560,6 @@
               (const_string "fop")))
    (set_attr "mode" "SF")])
 
-(define_insn "*fop_tf_5"
-  [(set (match_operand:TF 0 "register_operand" "=f,f")
-       (match_operator:TF 3 "binary_fp_operator"
-         [(match_operand:TF 1 "register_operand" "0,f")
-          (float_extend:TF
-           (match_operand 2 "nonimmediate_operand" "fm,0"))]))]
-  "TARGET_80387"
-  "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (cond [(match_operand:TF 3 "mult_operator" "") 
-                 (const_string "fmul")
-               (match_operand:TF 3 "div_operator" "") 
-                 (const_string "fdiv")
-              ]
-              (const_string "fop")))
-   (set_attr "mode" "SF")])
-
 (define_insn "*fop_xf_6"
   [(set (match_operand:XF 0 "register_operand" "=f,f")
        (match_operator:XF 3 "binary_fp_operator"
@@ -15291,7 +14567,7 @@
            (match_operand 1 "register_operand" "0,f"))
           (float_extend:XF
            (match_operand 2 "nonimmediate_operand" "fm,0"))]))]
-  "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
+  "TARGET_80387"
   "* return output_387_binary_op (insn, operands);"
   [(set (attr "type") 
         (cond [(match_operand:XF 3 "mult_operator" "") 
@@ -15302,24 +14578,6 @@
               (const_string "fop")))
    (set_attr "mode" "SF")])
 
-(define_insn "*fop_tf_6"
-  [(set (match_operand:TF 0 "register_operand" "=f,f")
-       (match_operator:TF 3 "binary_fp_operator"
-         [(float_extend:TF
-           (match_operand 1 "register_operand" "0,f"))
-          (float_extend:TF
-           (match_operand 2 "nonimmediate_operand" "fm,0"))]))]
-  "TARGET_80387"
-  "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (cond [(match_operand:TF 3 "mult_operator" "") 
-                 (const_string "fmul")
-               (match_operand:TF 3 "div_operator" "") 
-                 (const_string "fdiv")
-              ]
-              (const_string "fop")))
-   (set_attr "mode" "SF")])
-
 (define_split
   [(set (match_operand 0 "register_operand" "")
        (match_operator 3 "binary_fp_operator"
@@ -15457,17 +14715,7 @@
 (define_insn "sqrtxf2"
   [(set (match_operand:XF 0 "register_operand" "=f")
        (sqrt:XF (match_operand:XF 1 "register_operand" "0")))]
-  "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387 && !TARGET_NO_FANCY_MATH_387 
-   && (TARGET_IEEE_FP || flag_unsafe_math_optimizations) "
-  "fsqrt"
-  [(set_attr "type" "fpspc")
-   (set_attr "mode" "XF")
-   (set_attr "athlon_decode" "direct")])
-
-(define_insn "sqrttf2"
-  [(set (match_operand:TF 0 "register_operand" "=f")
-       (sqrt:TF (match_operand:TF 1 "register_operand" "0")))]
-  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 
+  "TARGET_80387 && !TARGET_NO_FANCY_MATH_387 
    && (TARGET_IEEE_FP || flag_unsafe_math_optimizations) "
   "fsqrt"
   [(set_attr "type" "fpspc")
@@ -15478,17 +14726,7 @@
   [(set (match_operand:XF 0 "register_operand" "=f")
        (sqrt:XF (float_extend:XF
                  (match_operand:DF 1 "register_operand" "0"))))]
-  "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387 && !TARGET_NO_FANCY_MATH_387"
-  "fsqrt"
-  [(set_attr "type" "fpspc")
-   (set_attr "mode" "XF")
-   (set_attr "athlon_decode" "direct")])
-
-(define_insn "*sqrtextenddftf2"
-  [(set (match_operand:TF 0 "register_operand" "=f")
-       (sqrt:TF (float_extend:TF
-                 (match_operand:DF 1 "register_operand" "0"))))]
-  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
+  "TARGET_80387 && !TARGET_NO_FANCY_MATH_387"
   "fsqrt"
   [(set_attr "type" "fpspc")
    (set_attr "mode" "XF")
@@ -15498,17 +14736,7 @@
   [(set (match_operand:XF 0 "register_operand" "=f")
        (sqrt:XF (float_extend:XF
                  (match_operand:SF 1 "register_operand" "0"))))]
-  "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387 && !TARGET_NO_FANCY_MATH_387"
-  "fsqrt"
-  [(set_attr "type" "fpspc")
-   (set_attr "mode" "XF")
-   (set_attr "athlon_decode" "direct")])
-
-(define_insn "*sqrtextendsftf2"
-  [(set (match_operand:TF 0 "register_operand" "=f")
-       (sqrt:TF (float_extend:TF
-                 (match_operand:SF 1 "register_operand" "0"))))]
-  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
+  "TARGET_80387 && !TARGET_NO_FANCY_MATH_387"
   "fsqrt"
   [(set_attr "type" "fpspc")
    (set_attr "mode" "XF")
@@ -15546,16 +14774,7 @@
 (define_insn "sinxf2"
   [(set (match_operand:XF 0 "register_operand" "=f")
        (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_SIN))]
-  "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387 && !TARGET_NO_FANCY_MATH_387
-   && flag_unsafe_math_optimizations"
-  "fsin"
-  [(set_attr "type" "fpspc")
-   (set_attr "mode" "XF")])
-
-(define_insn "sintf2"
-  [(set (match_operand:TF 0 "register_operand" "=f")
-       (unspec:TF [(match_operand:TF 1 "register_operand" "0")] UNSPEC_SIN))]
-  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 
+  "TARGET_80387 && !TARGET_NO_FANCY_MATH_387
    && flag_unsafe_math_optimizations"
   "fsin"
   [(set_attr "type" "fpspc")
@@ -15593,16 +14812,7 @@
 (define_insn "cosxf2"
   [(set (match_operand:XF 0 "register_operand" "=f")
        (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_COS))]
-  "!TARGET_128BIT_LONG_DOUBLE && ! TARGET_NO_FANCY_MATH_387 && TARGET_80387
-   && flag_unsafe_math_optimizations"
-  "fcos"
-  [(set_attr "type" "fpspc")
-   (set_attr "mode" "XF")])
-
-(define_insn "costf2"
-  [(set (match_operand:TF 0 "register_operand" "=f")
-       (unspec:TF [(match_operand:TF 1 "register_operand" "0")] UNSPEC_COS))]
-  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 
+  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
    && flag_unsafe_math_optimizations"
   "fcos"
   [(set_attr "type" "fpspc")
@@ -15665,7 +14875,7 @@
                   UNSPEC_FPATAN))
    (clobber (match_scratch:XF 3 "=1"))]
   "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
-   && flag_unsafe_math_optimizations && ! TARGET_128BIT_LONG_DOUBLE"
+   && flag_unsafe_math_optimizations"
   "fpatan"
   [(set_attr "type" "fpspc")
    (set_attr "mode" "XF")])
@@ -15675,7 +14885,7 @@
    (use (match_operand:XF 2 "register_operand" "0"))
    (use (match_operand:XF 1 "register_operand" "u"))]
   "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
-   && flag_unsafe_math_optimizations && ! TARGET_128BIT_LONG_DOUBLE"
+   && flag_unsafe_math_optimizations"
 {
   rtx copy = gen_reg_rtx (XFmode);
   emit_move_insn (copy, operands[1]);
@@ -15683,40 +14893,14 @@
   DONE;
 })
 
-(define_insn "atan2tf3_1"
-  [(set (match_operand:TF 0 "register_operand" "=f")
-        (unspec:TF [(match_operand:TF 2 "register_operand" "0")
-                   (match_operand:TF 1 "register_operand" "u")]
-                  UNSPEC_FPATAN))
-   (clobber (match_scratch:TF 3 "=1"))]
-  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
-   && flag_unsafe_math_optimizations && TARGET_128BIT_LONG_DOUBLE"
-  "fpatan"
-  [(set_attr "type" "fpspc")
-   (set_attr "mode" "XF")])
-
-(define_expand "atan2tf3"
-  [(use (match_operand:TF 0 "register_operand" "=f"))
-   (use (match_operand:TF 2 "register_operand" "0"))
-   (use (match_operand:TF 1 "register_operand" "u"))]
-  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
-   && flag_unsafe_math_optimizations && TARGET_128BIT_LONG_DOUBLE"
-{
-  rtx copy = gen_reg_rtx (TFmode);
-  emit_move_insn (copy, operands[1]);
-  emit_insn (gen_atan2tf3_1 (operands[0], copy, operands[2]));
-  DONE;
-})
-
 (define_insn "*fyl2x_sfxf3"
   [(set (match_operand:SF 0 "register_operand" "=f")
          (unspec:SF [(match_operand:SF 2 "register_operand" "0")
-                    (match_operand 1 "register_operand" "u")]
+                    (match_operand:XF 1 "register_operand" "u")]
                    UNSPEC_FYL2X))
    (clobber (match_scratch:SF 3 "=1"))]
   "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
-   && flag_unsafe_math_optimizations
-   && GET_MODE (operands[1]) == (TARGET_128BIT_LONG_DOUBLE ? TFmode : XFmode)"
+   && flag_unsafe_math_optimizations"
   "fyl2x"
   [(set_attr "type" "fpspc")
    (set_attr "mode" "SF")])
@@ -15724,12 +14908,11 @@
 (define_insn "*fyl2x_dfxf3"
   [(set (match_operand:DF 0 "register_operand" "=f")
          (unspec:DF [(match_operand:DF 2 "register_operand" "0")
-                    (match_operand 1 "register_operand" "u")]
+                    (match_operand:XF 1 "register_operand" "u")]
                    UNSPEC_FYL2X))
    (clobber (match_scratch:DF 3 "=1"))]
   "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
-   && flag_unsafe_math_optimizations
-   && GET_MODE (operands[1]) == (TARGET_128BIT_LONG_DOUBLE ? TFmode : XFmode)"
+   && flag_unsafe_math_optimizations"
   "fyl2x"
   [(set_attr "type" "fpspc")
    (set_attr "mode" "DF")])
@@ -15741,19 +14924,7 @@
                   UNSPEC_FYL2X))
    (clobber (match_scratch:XF 3 "=1"))]
   "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
-   && flag_unsafe_math_optimizations && !TARGET_128BIT_LONG_DOUBLE"
-  "fyl2x"
-  [(set_attr "type" "fpspc")
-   (set_attr "mode" "XF")])
-
-(define_insn "*fyl2x_tfxf3"
-  [(set (match_operand:TF 0 "register_operand" "=f")
-       (unspec:TF [(match_operand:TF 2 "register_operand" "0")
-                   (match_operand:TF 1 "register_operand" "u")]
-                   UNSPEC_FYL2X))
-   (clobber (match_scratch:TF 3 "=1"))]
-  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
-   && flag_unsafe_math_optimizations && TARGET_128BIT_LONG_DOUBLE"
+   && flag_unsafe_math_optimizations"
   "fyl2x"
   [(set_attr "type" "fpspc")
    (set_attr "mode" "XF")])
@@ -15768,7 +14939,7 @@
 {
   rtx temp;
 
-  operands[2] = gen_reg_rtx (TARGET_128BIT_LONG_DOUBLE ? TFmode : XFmode);
+  operands[2] = gen_reg_rtx (XFmode);
   temp = standard_80387_constant_rtx (4); /* fldln2 */
   emit_move_insn (operands[2], temp);
 })
@@ -15783,7 +14954,7 @@
 {
   rtx temp;
 
-  operands[2] = gen_reg_rtx (TARGET_128BIT_LONG_DOUBLE ? TFmode : XFmode);
+  operands[2] = gen_reg_rtx (XFmode);
   temp = standard_80387_constant_rtx (4); /* fldln2 */
   emit_move_insn (operands[2], temp);
 })
@@ -15794,7 +14965,7 @@
                               (match_dup 2)] UNSPEC_FYL2X))
              (clobber (match_scratch:XF 3 ""))])]
   "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
-   && flag_unsafe_math_optimizations && !TARGET_128BIT_LONG_DOUBLE"
+   && flag_unsafe_math_optimizations"
 {
   rtx temp;
 
@@ -15803,45 +14974,26 @@
   emit_move_insn (operands[2], temp);
 })
 
-(define_expand "logtf2"
-  [(parallel [(set (match_operand:TF 0 "register_operand" "")
-                  (unspec:TF [(match_operand:TF 1 "register_operand" "")
-                              (match_dup 2)] UNSPEC_FYL2X))
-             (clobber (match_scratch:TF 3 ""))])]
-  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
-   && flag_unsafe_math_optimizations && TARGET_128BIT_LONG_DOUBLE"
-{
-  rtx temp;
-
-  operands[2] = gen_reg_rtx (TFmode);
-  temp = standard_80387_constant_rtx (4); /* fldln2 */
-  emit_move_insn (operands[2], temp);
-})
-
 (define_insn "*fscale_sfxf3"
   [(set (match_operand:SF 0 "register_operand" "=f")
-        (unspec:SF [(match_operand 2 "register_operand" "0")
-                    (match_operand 1 "register_operand" "u")]
+        (unspec:SF [(match_operand:XF 2 "register_operand" "0")
+                    (match_operand:XF 1 "register_operand" "u")]
                    UNSPEC_FSCALE))
    (clobber (match_scratch:SF 3 "=1"))]
   "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
-   && flag_unsafe_math_optimizations
-   && GET_MODE (operands[1]) == (TARGET_128BIT_LONG_DOUBLE ? TFmode : XFmode)
-   && GET_MODE (operands[2]) == (TARGET_128BIT_LONG_DOUBLE ? TFmode : XFmode)"
+   && flag_unsafe_math_optimizations"
   "fscale\;fstp\t%y1"
   [(set_attr "type" "fpspc")
    (set_attr "mode" "SF")])
 
 (define_insn "*fscale_dfxf3"
   [(set (match_operand:DF 0 "register_operand" "=f")
-        (unspec:DF [(match_operand 2 "register_operand" "0")
-                    (match_operand 1 "register_operand" "u")]
+        (unspec:DF [(match_operand:XF 2 "register_operand" "0")
+                    (match_operand:XF 1 "register_operand" "u")]
                    UNSPEC_FSCALE))
    (clobber (match_scratch:DF 3 "=1"))]
   "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
-   && flag_unsafe_math_optimizations
-   && GET_MODE (operands[1]) == (TARGET_128BIT_LONG_DOUBLE ? TFmode : XFmode)
-   && GET_MODE (operands[2]) == (TARGET_128BIT_LONG_DOUBLE ? TFmode : XFmode)"
+   && flag_unsafe_math_optimizations"
   "fscale\;fstp\t%y1"
   [(set_attr "type" "fpspc")
    (set_attr "mode" "DF")])
@@ -15853,19 +15005,7 @@
                   UNSPEC_FSCALE))
    (clobber (match_scratch:XF 3 "=1"))]
   "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
-   && flag_unsafe_math_optimizations && !TARGET_128BIT_LONG_DOUBLE"
-  "fscale\;fstp\t%y1"
-  [(set_attr "type" "fpspc")
-   (set_attr "mode" "XF")])
-
-(define_insn "*fscale_tf3"
-  [(set (match_operand:TF 0 "register_operand" "=f")
-       (unspec:TF [(match_operand:TF 2 "register_operand" "0")
-                   (match_operand:TF 1 "register_operand" "u")]
-                  UNSPEC_FSCALE))
-   (clobber (match_scratch:TF 3 "=1"))]
-  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
-   && flag_unsafe_math_optimizations && TARGET_128BIT_LONG_DOUBLE"
+   && flag_unsafe_math_optimizations"
   "fscale\;fstp\t%y1"
   [(set_attr "type" "fpspc")
    (set_attr "mode" "XF")])
@@ -15875,17 +15015,7 @@
        (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
         UNSPEC_FRNDINT))]
   "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
-   && flag_unsafe_math_optimizations && !TARGET_128BIT_LONG_DOUBLE"
-  "frndint"
-  [(set_attr "type" "fpspc")
-   (set_attr "mode" "XF")])
-
-(define_insn "*frndinttf2"
-  [(set (match_operand:TF 0 "register_operand" "=f")
-       (unspec:TF [(match_operand:TF 1 "register_operand" "0")]
-        UNSPEC_FRNDINT))]
-  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
-   && flag_unsafe_math_optimizations && TARGET_128BIT_LONG_DOUBLE"
+   && flag_unsafe_math_optimizations"
   "frndint"
   [(set_attr "type" "fpspc")
    (set_attr "mode" "XF")])
@@ -15895,17 +15025,7 @@
        (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
         UNSPEC_F2XM1))]
   "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
-   && flag_unsafe_math_optimizations && !TARGET_128BIT_LONG_DOUBLE"
-  "f2xm1"
-  [(set_attr "type" "fpspc")
-   (set_attr "mode" "XF")])
-
-(define_insn "*f2xm1tf2"
-  [(set (match_operand:TF 0 "register_operand" "=f")
-       (unspec:TF [(match_operand:TF 1 "register_operand" "0")]
-        UNSPEC_F2XM1))]
-  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
-   && flag_unsafe_math_optimizations && TARGET_128BIT_LONG_DOUBLE"
+   && flag_unsafe_math_optimizations"
   "f2xm1"
   [(set_attr "type" "fpspc")
    (set_attr "mode" "XF")])
@@ -15927,12 +15047,6 @@
   rtx temp;
   int i;
 
-  if (TARGET_128BIT_LONG_DOUBLE)
-    {
-      emit_insn (gen_expsf2_tf (operands[0], operands[1]));
-      DONE;
-    }
-
   for (i=2; i<10; i++)
     operands[i] = gen_reg_rtx (XFmode);
   temp = standard_80387_constant_rtx (5); /* fldl2e */
@@ -15940,29 +15054,6 @@
   emit_move_insn (operands[8], CONST1_RTX (XFmode));  /* fld1 */
 })
 
-(define_expand "expsf2_tf"
-  [(set (match_dup 2)
-       (float_extend:TF (match_operand:SF 1 "register_operand" "")))
-   (set (match_dup 4) (mult:TF (match_dup 2) (match_dup 3)))
-   (set (match_dup 5) (unspec:TF [(match_dup 4)] UNSPEC_FRNDINT))
-   (set (match_dup 6) (minus:TF (match_dup 4) (match_dup 5)))
-   (set (match_dup 7) (unspec:TF [(match_dup 6)] UNSPEC_F2XM1))
-   (set (match_dup 9) (plus:TF (match_dup 7) (match_dup 8)))
-   (parallel [(set (match_operand:SF 0 "register_operand" "")
-                  (unspec:SF [(match_dup 9) (match_dup 5)] UNSPEC_FSCALE))
-             (clobber (match_scratch:SF 5 ""))])]
-  ""
-{
-  rtx temp;
-  int i;
-
-  for (i=2; i<10; i++)
-    operands[i] = gen_reg_rtx (TFmode);
-  temp = standard_80387_constant_rtx (5); /* fldl2e */
-  emit_move_insn (operands[3], temp);
-  emit_move_insn (operands[8], CONST1_RTX (TFmode));  /* fld1 */
-})
-
 (define_expand "expdf2"
   [(set (match_dup 2)
        (float_extend:XF (match_operand:DF 1 "register_operand" "")))
@@ -15980,12 +15071,6 @@
   rtx temp;
   int i;
 
-  if (TARGET_128BIT_LONG_DOUBLE)
-    {
-      emit_insn (gen_expdf2_tf (operands[0], operands[1]));
-      DONE;
-    }
-
   for (i=2; i<10; i++)
     operands[i] = gen_reg_rtx (XFmode);
   temp = standard_80387_constant_rtx (5); /* fldl2e */
@@ -15993,30 +15078,6 @@
   emit_move_insn (operands[8], CONST1_RTX (XFmode));  /* fld1 */
 })
 
-
-(define_expand "expdf2_tf"
-  [(set (match_dup 2)
-       (float_extend:TF (match_operand:DF 1 "register_operand" "")))
-   (set (match_dup 4) (mult:TF (match_dup 2) (match_dup 3)))
-   (set (match_dup 5) (unspec:TF [(match_dup 4)] UNSPEC_FRNDINT))
-   (set (match_dup 6) (minus:TF (match_dup 4) (match_dup 5)))
-   (set (match_dup 7) (unspec:TF [(match_dup 6)] UNSPEC_F2XM1))
-   (set (match_dup 9) (plus:TF (match_dup 7) (match_dup 8)))
-   (parallel [(set (match_operand:DF 0 "register_operand" "")
-                  (unspec:DF [(match_dup 9) (match_dup 5)] UNSPEC_FSCALE))
-             (clobber (match_scratch:DF 5 ""))])]
-   ""
-{
-  rtx temp;
-  int i;
-
-  for (i=2; i<10; i++)
-    operands[i] = gen_reg_rtx (TFmode);
-  temp = standard_80387_constant_rtx (5); /* fldl2e */
-  emit_move_insn (operands[3], temp);
-  emit_move_insn (operands[8], CONST1_RTX (TFmode));  /* fld1 */
-})
-
 (define_expand "expxf2"
   [(set (match_dup 3) (mult:XF (match_operand:XF 1 "register_operand" "")
                               (match_dup 2)))
@@ -16028,7 +15089,7 @@
                   (unspec:XF [(match_dup 8) (match_dup 4)] UNSPEC_FSCALE))
              (clobber (match_scratch:XF 5 ""))])]
   "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
-   && flag_unsafe_math_optimizations && !TARGET_128BIT_LONG_DOUBLE"
+   && flag_unsafe_math_optimizations"
 {
   rtx temp;
   int i;
@@ -16053,29 +15114,6 @@
   emit_move_insn (operands[2], CONST1_RTX (SFmode));  /* fld1 */
 })
 
-(define_expand "exptf2"
-  [(set (match_dup 3) (mult:TF (match_operand:TF 1 "register_operand" "")
-                              (match_dup 2)))
-   (set (match_dup 4) (unspec:TF [(match_dup 3)] UNSPEC_FRNDINT))
-   (set (match_dup 5) (minus:TF (match_dup 3) (match_dup 4)))
-   (set (match_dup 6) (unspec:TF [(match_dup 5)] UNSPEC_F2XM1))
-   (set (match_dup 8) (plus:TF (match_dup 6) (match_dup 7)))
-   (parallel [(set (match_operand:TF 0 "register_operand" "")
-                  (unspec:TF [(match_dup 8) (match_dup 4)] UNSPEC_FSCALE))
-             (clobber (match_scratch:TF 5 ""))])]
-  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
-   && flag_unsafe_math_optimizations && TARGET_128BIT_LONG_DOUBLE"
-{
-  rtx temp;
-  int i;
-
-  for (i=2; i<9; i++)
-    operands[i] = gen_reg_rtx (TFmode);
-  temp = standard_80387_constant_rtx (5); /* fldl2e */
-  emit_move_insn (operands[2], temp);
-  emit_move_insn (operands[7], CONST1_RTX (TFmode));  /* fld1 */
-})
-
 (define_expand "atandf2"
   [(parallel [(set (match_operand:DF 0 "register_operand" "")
                   (unspec:DF [(match_dup 2)
@@ -16096,24 +15134,11 @@
                    UNSPEC_FPATAN))
              (clobber (match_scratch:XF 3 ""))])]
   "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
-   && flag_unsafe_math_optimizations && !TARGET_128BIT_LONG_DOUBLE"
+   && flag_unsafe_math_optimizations"
 {
   operands[2] = gen_reg_rtx (XFmode);
   emit_move_insn (operands[2], CONST1_RTX (XFmode));  /* fld1 */
 })
-
-(define_expand "atantf2"
-  [(parallel [(set (match_operand:TF 0 "register_operand" "")
-                  (unspec:TF [(match_dup 2)
-                              (match_operand:TF 1 "register_operand" "")]
-                   UNSPEC_FPATAN))
-             (clobber (match_scratch:TF 3 ""))])]
-  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
-   && flag_unsafe_math_optimizations && TARGET_128BIT_LONG_DOUBLE"
-{
-  operands[2] = gen_reg_rtx (TFmode);
-  emit_move_insn (operands[2], CONST1_RTX (TFmode));  /* fld1 */
-})
 \f
 ;; Block operation instructions
 
@@ -17364,14 +16389,6 @@
        (if_then_else:XF (match_operand 1 "comparison_operator" "")
                         (match_operand:XF 2 "register_operand" "")
                         (match_operand:XF 3 "register_operand" "")))]
-  "!TARGET_128BIT_LONG_DOUBLE && TARGET_CMOVE"
-  "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
-
-(define_expand "movtfcc"
-  [(set (match_operand:TF 0 "register_operand" "")
-       (if_then_else:TF (match_operand 1 "comparison_operator" "")
-                        (match_operand:TF 2 "register_operand" "")
-                        (match_operand:TF 3 "register_operand" "")))]
   "TARGET_CMOVE"
   "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
 
@@ -17381,19 +16398,6 @@
                                [(reg 17) (const_int 0)])
                      (match_operand:XF 2 "register_operand" "f,0")
                      (match_operand:XF 3 "register_operand" "0,f")))]
-  "!TARGET_128BIT_LONG_DOUBLE && TARGET_CMOVE"
-  "@
-   fcmov%F1\t{%2, %0|%0, %2}
-   fcmov%f1\t{%3, %0|%0, %3}"
-  [(set_attr "type" "fcmov")
-   (set_attr "mode" "XF")])
-
-(define_insn "*movtfcc_1"
-  [(set (match_operand:TF 0 "register_operand" "=f,f")
-       (if_then_else:TF (match_operator 1 "fcmov_comparison_operator" 
-                               [(reg 17) (const_int 0)])
-                     (match_operand:TF 2 "register_operand" "f,0")
-                     (match_operand:TF 3 "register_operand" "0,f")))]
   "TARGET_CMOVE"
   "@
    fcmov%F1\t{%2, %0|%0, %2}
@@ -19534,6 +18538,18 @@
   DONE;
 })
 
+(define_expand "movtf"
+  [(set (match_operand:TF 0 "nonimmediate_operand" "")
+       (match_operand:TF 1 "nonimmediate_operand" ""))]
+  "TARGET_64BIT"
+{
+  if (TARGET_64BIT)
+    ix86_expand_move (TFmode, operands);
+  else
+    ix86_expand_vector_move (TFmode, operands);
+  DONE;
+})
+
 (define_insn "movv2df_internal"
   [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,m")
        (match_operand:V2DF 1 "vector_move_operand" "C,xm,x"))]
@@ -19919,6 +18935,50 @@
                   (const_string "TI"))]
               (const_string "DI")))])
 
+(define_insn "*movtf_rex64"
+  [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o,x,x,xm")
+       (match_operand:TF 1 "general_operand" "riFo,riF,C,xm,x"))]
+  "TARGET_64BIT
+   && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
+{
+  switch (which_alternative)
+    {
+    case 0:
+    case 1:
+      return "#";
+    case 2:
+      if (get_attr_mode (insn) == MODE_V4SF)
+       return "xorps\t%0, %0";
+      else
+       return "pxor\t%0, %0";
+    case 3:
+    case 4:
+      if (get_attr_mode (insn) == MODE_V4SF)
+       return "movaps\t{%1, %0|%0, %1}";
+      else
+       return "movdqa\t{%1, %0|%0, %1}";
+    default:
+      abort ();
+    }
+}
+  [(set_attr "type" "*,*,ssemov,ssemov,ssemov")
+   (set (attr "mode")
+        (cond [(eq_attr "alternative" "2,3")
+                (if_then_else
+                  (ne (symbol_ref "optimize_size")
+                      (const_int 0))
+                  (const_string "V4SF")
+                  (const_string "TI"))
+              (eq_attr "alternative" "4")
+                (if_then_else
+                  (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
+                           (const_int 0))
+                       (ne (symbol_ref "optimize_size")
+                           (const_int 0)))
+                  (const_string "V4SF")
+                  (const_string "TI"))]
+              (const_string "DI")))])
+
 (define_split
   [(set (match_operand:TI 0 "nonimmediate_operand" "")
         (match_operand:TI 1 "general_operand" ""))]
@@ -19927,6 +18987,14 @@
   [(const_int 0)]
   "ix86_split_long_move (operands); DONE;")
 
+(define_split
+  [(set (match_operand:TF 0 "nonimmediate_operand" "")
+        (match_operand:TF 1 "general_operand" ""))]
+  "reload_completed && !SSE_REG_P (operands[0])
+   && !SSE_REG_P (operands[1])"
+  [(const_int 0)]
+  "ix86_split_long_move (operands); DONE;")
+
 ;; These two patterns are useful for specifying exactly whether to use
 ;; movaps or movups
 (define_expand "sse_movaps"

diff --git a/gcc/real.c b/gcc/real.c
index 87246807f2f3428d4c0cf575a141359b7290dbf1..0801054611536d0daa5bc9afa0de73fc49d93d1e 100644 (file)
--- a/gcc/real.c
+++ b/gcc/real.c
@@ -3032,6 +3032,11 @@ encode_ieee_extended (const struct real_format *fmt, long *buf,
     buf[0] = image_hi << 16, buf[1] = sig_hi, buf[2] = sig_lo;
   else
     buf[0] = sig_lo, buf[1] = sig_hi, buf[2] = image_hi;
+
+  /* Avoid uninitialized data to be output by compiler when XFmode is extended
+     to 128 bits.  */
+  if (GET_MODE_SIZE (XFmode) == 16)
+    buf[3] = 0;
 }
 
 static void

diff --git a/gcc/reg-stack.c b/gcc/reg-stack.c
index 50bc63fcb0c6c90873b98e9872f7058564630d25..08d26f60c32669422c3e179157c1f82f73ef78d2 100644 (file)
--- a/gcc/reg-stack.c
+++ b/gcc/reg-stack.c
@@ -1124,7 +1124,7 @@ move_for_stack_reg (rtx insn, stack regstack, rtx pat)
          regstack->top--;
          CLEAR_HARD_REG_BIT (regstack->reg_set, REGNO (src));
        }
-      else if ((GET_MODE (src) == XFmode || GET_MODE (src) == TFmode)
+      else if ((GET_MODE (src) == XFmode)
               && regstack->top < REG_STACK_SIZE - 1)
        {
          /* A 387 cannot write an XFmode value to a MEM without
@@ -1137,10 +1137,7 @@ move_for_stack_reg (rtx insn, stack regstack, rtx pat)
          rtx push_rtx, push_insn;
          rtx top_stack_reg = FP_MODE_REG (FIRST_STACK_REG, GET_MODE (src));
 
-         if (GET_MODE (src) == TFmode)
-           push_rtx = gen_movtf (top_stack_reg, top_stack_reg);
-         else
-           push_rtx = gen_movxf (top_stack_reg, top_stack_reg);
+         push_rtx = gen_movxf (top_stack_reg, top_stack_reg);
          push_insn = emit_insn_before (push_rtx, insn);
          REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_DEAD, top_stack_reg,
                                                REG_NOTES (insn));