swr/rast: disable AVX512 optimization of SSE / AVX code

Disable an optimization which implemented sse/avx operations on avx512
using avx512 intrinsics (to avoid switching between lane widths).

Compile with SIMD_OPT_128_AVX512 / SIMD_OPT_256_AVX512 defined to enable
these optimizations.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

diff --git a/src/gallium/drivers/swr/rasterizer/common/simdlib.hpp b/src/gallium/drivers/swr/rasterizer/common/simdlib.hpp
index 0c79cdd660599f837fa983768aeddd5055c98ed6..a4b5854d004dc9222e00d7364a859ad84cba8d2c 100644 (file)
--- a/src/gallium/drivers/swr/rasterizer/common/simdlib.hpp
+++ b/src/gallium/drivers/swr/rasterizer/common/simdlib.hpp
@@ -53,6 +53,7 @@ namespace SIMDImpl
 #if SIMD_ARCH >= SIMD_ARCH_AVX512
         struct AVX512Impl : AVX2Impl
         {
+#if defined(SIMD_OPT_128_AVX512)
 #define __SIMD_LIB_AVX512_HPP__
 #include "simdlib_128_avx512.inl"
 #if defined(SIMD_ARCH_KNIGHTS)
@@ -61,6 +62,7 @@ namespace SIMDImpl
 #include "simdlib_128_avx512_core.inl"
 #endif // defined(SIMD_ARCH_KNIGHTS)
 #undef __SIMD_LIB_AVX512_HPP__
+#endif // SIMD_OPT_128_AVX512
         }; // struct AVX2Impl
 #endif // #if SIMD_ARCH >= SIMD_ARCH_AVX512
 
@@ -108,6 +110,7 @@ namespace SIMDImpl
 #if SIMD_ARCH >= SIMD_ARCH_AVX512
         struct AVX512Impl : AVX2Impl
         {
+#if defined(SIMD_OPT_256_AVX512)
 #define __SIMD_LIB_AVX512_HPP__
 #include "simdlib_256_avx512.inl"
 #if defined(SIMD_ARCH_KNIGHTS)
@@ -116,6 +119,7 @@ namespace SIMDImpl
 #include "simdlib_256_avx512_core.inl"
 #endif // defined(SIMD_ARCH_KNIGHTS)
 #undef __SIMD_LIB_AVX512_HPP__
+#endif // SIMD_OPT_256_AVX512
         }; // struct AVX2Impl
 #endif // #if SIMD_ARCH >= SIMD_ARCH_AVX512