Fix PR 26000, logical bitwise error / prologue analyzer

This fixes an instruction mask typo. We should be matching only
ldrd (immediate) and not any other of its variants. As is, it never matches
anything.

With the patch, the instruction mask also allows matching of ldrd (literal),
but the check for SP discards this particular instruction pattern, as it has
a hardcoded PC register.

gdb/ChangeLog:

2020-05-27  Luis Machado  <luis.machado@linaro.org>

	PR tdep/26000
	* arm-tdep.c (thumb_analyze_prologue): Fix instruction matching
	for ldrd (immediate).

diff --git a/gdb/ChangeLog b/gdb/ChangeLog
index b0ec14fd4f98ef9384bb816486289b3c9938ceee..6cadd332324bf3e67bdc05c0fcb41bbd1c6bf2ac 100644 (file)
--- a/gdb/ChangeLog
+++ b/gdb/ChangeLog
@@ -1,3 +1,9 @@
+2020-05-27  Luis Machado  <luis.machado@linaro.org>
+
+       PR tdep/26000
+       * arm-tdep.c (thumb_analyze_prologue): Fix instruction matching
+       for ldrd (immediate).
+
 2020-05-26  Philippe Waroquiers  <philippe.waroquiers@skynet.be>
 
        * command.h: Add comment giving the name of class_tui.

diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
index 3e085245c8e85ea0d0549fb6986e33f690b0c204..5c5efe52e6ead56d2284338425c0deac906e25a1 100644 (file)
--- a/gdb/arm-tdep.c
+++ b/gdb/arm-tdep.c
@@ -931,7 +931,7 @@ thumb_analyze_prologue (struct gdbarch *gdbarch,
               parameters from memory.  */
            ;
 
-         else if ((insn & 0xffb0) == 0xe950    /* ldrd Rt, Rt2,
+         else if ((insn & 0xff70) == 0xe950    /* ldrd Rt, Rt2,
                                                   [Rn, #+/-imm] */
                   && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
            /* Similarly ignore dual loads from the stack.  */