sse.md (vec_initv4sf): Removed.

2008-05-21  H.J. Lu  <hongjiu.lu@intel.com>

	* config/i386/sse.md (vec_initv4sf): Removed.
	(vec_initv2df): Likewise.
	(vec_initv2di): Likewise.
	(vec_initv4si): Likewise.
	(vec_initv8hi): Likewise.
	(vec_initv16qi): Likewise.
	(vec_init<mode>): New.

From-SVN: r135724

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 1d13768cf5b70cf43ebbb48e4ad4da04bab4744d..b686fe5db7fec1f24766b3e8c45342eb49d14c38 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,13 @@
+2008-05-21  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * config/i386/sse.md (vec_initv4sf): Removed.
+       (vec_initv2df): Likewise.
+       (vec_initv2di): Likewise.
+       (vec_initv4si): Likewise.
+       (vec_initv8hi): Likewise.
+       (vec_initv16qi): Likewise.
+       (vec_init<mode>): New.
+
 2008-05-21  Joseph Myers  <joseph@codesourcery.com>
 
        * collect2.c (find_a_file): Use IS_ABSOLUTE_PATH.

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index f767ddafc04aa0b91088487c950d26361abe5561..b2aba5126c548f66d367340c2d704a528fdebaec 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -2304,8 +2304,8 @@
   [(set_attr "type" "ssemov")
    (set_attr "mode" "V4SF,V2SF")])
 
-(define_expand "vec_initv4sf"
-  [(match_operand:V4SF 0 "register_operand" "")
+(define_expand "vec_init<mode>"
+  [(match_operand:SSEMODE 0 "register_operand" "")
    (match_operand 1 "" "")]
   "TARGET_SSE"
 {
@@ -2808,15 +2808,6 @@
   DONE;
 })
 
-(define_expand "vec_initv2df"
-  [(match_operand:V2DF 0 "register_operand" "")
-   (match_operand 1 "" "")]
-  "TARGET_SSE"
-{
-  ix86_expand_vector_init (false, operands[0], operands[1]);
-  DONE;
-})
-
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;;
 ;; Parallel integral arithmetic
@@ -4952,15 +4943,6 @@
   DONE;
 })
 
-(define_expand "vec_initv2di"
-  [(match_operand:V2DI 0 "register_operand" "")
-   (match_operand 1 "" "")]
-  "TARGET_SSE"
-{
-  ix86_expand_vector_init (false, operands[0], operands[1]);
-  DONE;
-})
-
 (define_expand "vec_setv4si"
   [(match_operand:V4SI 0 "register_operand" "")
    (match_operand:SI 1 "register_operand" "")
@@ -4983,15 +4965,6 @@
   DONE;
 })
 
-(define_expand "vec_initv4si"
-  [(match_operand:V4SI 0 "register_operand" "")
-   (match_operand 1 "" "")]
-  "TARGET_SSE"
-{
-  ix86_expand_vector_init (false, operands[0], operands[1]);
-  DONE;
-})
-
 (define_expand "vec_setv8hi"
   [(match_operand:V8HI 0 "register_operand" "")
    (match_operand:HI 1 "register_operand" "")
@@ -5014,15 +4987,6 @@
   DONE;
 })
 
-(define_expand "vec_initv8hi"
-  [(match_operand:V8HI 0 "register_operand" "")
-   (match_operand 1 "" "")]
-  "TARGET_SSE"
-{
-  ix86_expand_vector_init (false, operands[0], operands[1]);
-  DONE;
-})
-
 (define_expand "vec_setv16qi"
   [(match_operand:V16QI 0 "register_operand" "")
    (match_operand:QI 1 "register_operand" "")
@@ -5045,15 +5009,6 @@
   DONE;
 })
 
-(define_expand "vec_initv16qi"
-  [(match_operand:V16QI 0 "register_operand" "")
-   (match_operand 1 "" "")]
-  "TARGET_SSE"
-{
-  ix86_expand_vector_init (false, operands[0], operands[1]);
-  DONE;
-})
-
 (define_expand "vec_unpacku_hi_v16qi"
   [(match_operand:V8HI 0 "register_operand" "")
    (match_operand:V16QI 1 "register_operand" "")]