(no commit message)

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index e0c0a9ee03b94ead03ec7ec0ea7b4bd60e73d4cc..46e9578be12ec25e229a671e41918141affbaff8 100644 (file)
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -551,9 +551,11 @@ sequentially through these registers (LSB0 sequential ordering from 0
 to VL-1).
 
 Where the integer regfile in standard scalar Power ISA v3.0B/v3.1B is
-r0 to r31, SV extends this as r0 to r127.  Likewise FP registers are
+r0 to r31, SV extends this range (in the Upper Compliancy Levels of SV)
+as r0 to r127.  Likewise FP registers are
 extended to 128 (fp0 to fp127), and CR Fields are extended to 128 entries,
-CR0 thru CR127.
+CR0 thru CR127.  In the Lower SV Compliancy Levels the quantity of regiaters
+remains the same in order to reduce implementation cost for Embedded systems.
 
 The names of the registers therefore reflects a simple linear extension
 of the Power ISA v3.0B / v3.1B register naming, and in hardware this