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Move lookup inside if
author
Eddie Hung
<eddieh@ece.ubc.ca>
Fri, 15 Feb 2019 23:23:26 +0000
(15:23 -0800)
committer
Eddie Hung
<eddieh@ece.ubc.ca>
Fri, 15 Feb 2019 23:23:26 +0000
(15:23 -0800)
passes/techmap/abc9.cc
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diff --git
a/passes/techmap/abc9.cc
b/passes/techmap/abc9.cc
index b32facc4896cbb03a4d208f5cfbd95118a99a606..492911177d49afe3842f21dff90336b1336152ee 100644
(file)
--- a/
passes/techmap/abc9.cc
+++ b/
passes/techmap/abc9.cc
@@
-455,9
+455,9
@@
void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
RTLIL::Wire *remap_wire = module->addWire(remap_name(w->name), GetSize(w));
if (markgroups) remap_wire->attributes["\\abcgroup"] = map_autoidx;
design->select(module, remap_wire);
- RTLIL::Wire *wire = module->wire(w->name);
if (w->port_output) {
- for (int i = 0; i < GetSize(remap_wire); i++)
+ RTLIL::Wire *wire = module->wire(w->name);
+ for (int i = 0; i < GetSize(wire); i++)
output_bits.insert({wire, i});
}
}