Wishbone: omit fixed LSBs

diff --git a/milkymist/lm32/__init__.py b/milkymist/lm32/__init__.py
index 4425fcbdb93d8c0e7827b21aa3334c73a5805f74..26b47947ef2fb8543aec8f475a0cc74db5538ebb 100644 (file)
--- a/milkymist/lm32/__init__.py
+++ b/milkymist/lm32/__init__.py
@@ -8,7 +8,7 @@ class Inst:
                self.interrupt = Signal(BV(32))
                self.ext_break = Signal()
                self._inst = Instance("lm32_top",
-                       [("I_ADR_O", i.adr_o),
+                       [("I_ADR_O", BV(32)),
                        ("I_DAT_O", i.dat_o),
                        ("I_SEL_O", i.sel_o),
                        ("I_CYC_O", i.cyc_o),
@@ -17,7 +17,7 @@ class Inst:
                        ("I_CTI_O", i.cti_o),
                        ("I_LOCK_O", BV(1)),
                        ("I_BTE_O", i.bte_o),
-                       ("D_ADR_O", d.adr_o),
+                       ("D_ADR_O", BV(32)),
                        ("D_DAT_O", d.dat_o),
                        ("D_SEL_O", d.sel_o),
                        ("D_CYC_O", d.cyc_o),
@@ -44,6 +44,8 @@ class Inst:
        def get_fragment(self):
                comb = [
                        self._inst.ins["I_RTY_I"].eq(0),
-                       self._inst.ins["D_RTY_I"].eq(0)
+                       self._inst.ins["D_RTY_I"].eq(0),
+                       self.ibus.adr_o.eq(self._inst.outs["I_ADR_O"][2:]),
+                       self.dbus.adr_o.eq(self._inst.outs["D_ADR_O"][2:])
                ]
                return Fragment(comb=comb, instances=[self._inst])

diff --git a/milkymist/norflash/__init__.py b/milkymist/norflash/__init__.py
index 93285fe58ee0231461d4d903cb2d61890409031a..ccb2c1f10e64d8e9e52f054ab585d137fdc9b8db 100644 (file)
--- a/milkymist/norflash/__init__.py
+++ b/milkymist/norflash/__init__.py
@@ -11,10 +11,10 @@ class Inst:
                self.we_n = Signal()
                self.ce_n = Signal()
                self.timeline = timeline.Inst(self.bus.cyc_i & self.bus.stb_i,
-                       [(0, [self.adr.eq(Cat(0, self.bus.adr_i[2:adr_width]))]),
+                       [(0, [self.adr.eq(Cat(0, self.bus.adr_i[:adr_width-2]))]),
                        (rd_timing, [
                                self.bus.dat_o[16:].eq(self.d),
-                               self.adr.eq(Cat(1, self.bus.adr_i[2:adr_width]))]),
+                               self.adr.eq(Cat(1, self.bus.adr_i[:adr_width-2]))]),
                        (2*rd_timing, [
                                self.bus.dat_o[:16].eq(self.d),
                                self.bus.ack_o.eq(1)]),