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Small opt
author
Eddie Hung
<eddie@fpgeh.com>
Thu, 11 Jul 2019 01:56:50 +0000
(18:56 -0700)
committer
Eddie Hung
<eddie@fpgeh.com>
Thu, 11 Jul 2019 01:56:50 +0000
(18:56 -0700)
frontends/aiger/aigerparse.cc
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diff --git
a/frontends/aiger/aigerparse.cc
b/frontends/aiger/aigerparse.cc
index 11c5e35700183b594015e585957b9c5c95fc1d57..b599160cf8eeb6174d1552ddf28827048a864eef 100644
(file)
--- a/
frontends/aiger/aigerparse.cc
+++ b/
frontends/aiger/aigerparse.cc
@@
-749,7
+749,6
@@
void AigerReader::post_process()
log_assert(box_module);
RTLIL::Module* flop_module = nullptr;
- const RTLIL::IdString flop_past_q = RTLIL::escape_id("\\$pastQ");
if (seen_boxes.insert(cell->type).second) {
auto it = box_module->attributes.find("\\abc_flop");
if (it != box_module->attributes.end()) {
@@
-830,7
+829,7
@@
void AigerReader::post_process()
rhs.append(wire);
}
- if (!flop_module || port_name !=
flop_past_q
)
+ if (!flop_module || port_name !=
"\\$pastQ"
)
cell->setPort(port_name, rhs);
}