i965: fix wrong cube/3D texture layout

Fix wrong cube/3D texture layout for the tailing levels whose width or
height is smaller than the align unit.

From 965 B-spec http://intellinuxgraphics.org/VOL_1_graphics_core.pdf at
page 135:
   All of the LOD=0 q-planes are stacked vertically, then below that,
   the LOD=1 qplanes are stacked two-wide, then the LOD=2 qplanes are
   stacked four-wide below that, and so on.

Thus we should always inrease pack_x_nr, which results to the pitch of LODn
may greater than the pitch of LOD0. So we should refactor mt->total_width
when needed.

This would fix the following webgl test case on all gen4 platforms:
  conformance/textures/texture-size-cube-maps.html

NOTE: This is a candidate for stable release branches.

Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>

diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 7a1b91f3721fd103e7416bd6f7b1292bd5178a4d..8bf1d3ddbcdd382014c42a7e4df6655341bbae3e 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -115,6 +115,8 @@ brw_miptree_layout(struct intel_context *intel, struct intel_mipmap_tree *mt)
               intel_miptree_set_image_offset(mt, level, q, x, y);
               x += pack_x_pitch;
            }
+            if (x > mt->total_width)
+               mt->total_width = x;
 
            x = 0;
            y += pack_y_pitch;
@@ -135,10 +137,9 @@ brw_miptree_layout(struct intel_context *intel, struct intel_mipmap_tree *mt)
               pack_x_nr <<= 1;
            }
         } else {
+            pack_x_nr <<= 1;
            if (pack_x_pitch > 4) {
               pack_x_pitch >>= 1;
-              pack_x_nr <<= 1;
-              assert(pack_x_pitch * pack_x_nr <= mt->total_width);
            }
 
            if (pack_y_pitch > 2) {