projects / openpower-isa.git / commitdiff
? search:
summary | shortlog | log | commit | commitdiff | tree
raw | patch | inline | side by side (parent: 32d3e7b)
fix dsrd pseudocode to use ROTL64 not ROTL128
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 28 Oct 2022 12:23:08 +0000 (13:23 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 28 Oct 2022 12:23:08 +0000 (13:23 +0100)
openpower/isa/svfixedarith.mdwn patch | blob | history

diff --git a/openpower/isa/svfixedarith.mdwn b/openpower/isa/svfixedarith.mdwn
index 0de85f2783351f6bb6e46a007c5caba77d665727..e8232c27e38be9b75373fcd946049fb98884ba3e 100644 (file)
--- a/openpower/isa/svfixedarith.mdwn
+++ b/openpower/isa/svfixedarith.mdwn
@@ -75,10 +75,10 @@ VA2-Form
 Pseudo-code:
 
     n <- (RB)[58:63]
-    v <- ROTL128((RA) || [0]*64, 128-n)
-    mask <- ¬MASK(n, 63)
-    RT <- v[0:63] | ((RC) & mask)
-    RS <- v[64:127]
+    v <- ROTL64((RA), 64-n)
+    mask <- MASK(n, 63)
+    RT <- (v[0:63] & mask) | ((RC) & ¬mask)
+    RS <- v[0:63] & ¬mask
 
 Special Registers Altered: