Re: [libre-riscv-dev] cache SRAM organisation

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+From: Staf Verhaegen <staf@fibraservi.eu>
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+Subject: Re: [libre-riscv-dev] cache SRAM organisation
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+Luke Kenneth Casson Leighton schreef op vr 27-03-2020 om 09:16 [+0000]:
+> On Fri, Mar 27, 2020 at 9:09 AM Staf Verhaegen <staf@fibraservi.eu> wrote=
+:
+> > I still feel you intermix synchronous and write-through in this stateme=
+nt, the above seems to be possible with synchronous SRAMs.
+>=20
+> this would be good.  what would help clarify immensely is if you couldlet=
+ us know what options to nmigen Memory class are "supported".then it is rea=
+lly clear.
+
+The nmigen Memory abstraction does not seem to allow a good representation =
+of a write-through SRAM. AFAICS it does not allow to have the output of the=
+ read port be changed by what you write on the write port.
+
+greets,
+Staf.
+
+
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