arch-arm: Implement AArch32 RVBAR

RVBAR has been added to the system register list since ARMv8.0-A.  It is
implemented only if the highest Exception Level is different (minor)
than EL3.  If that's not the case, MVBAR is used. Since the two
registers are mutually exclusive (depending on the presence of EL3),
they share the same coprocessor numbers:

p15, 0, c12, c0, 1

Rather than introducing a new register alias, we overload MVBAR so that
it is treated as RVBAR if ArmSystem::highestEL() < EL3. This patch is
changing the MiscReg info so that EL1 or EL2 access MVBAR (as RVBAR).

N.B MVBAR is RW, whereas RVBAR is RO

Change-Id: Ida3070413fd151ce79c446e99a2a389298d5f5bd
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13999
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 89c673e4bf18efb709e654c5319ab42c090e6588..65d2251f8ba989a4a0a883a747d7cb73358e96ec 100644 (file)
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -229,6 +229,11 @@ namespace ArmISA
                 privNonSecure(v);
                 return *this;
             }
+            chain privRead(bool v = true) const {
+                privSecureRead(v);
+                privNonSecureRead(v);
+                return *this;
+            }
             chain hypRead(bool v = true) const {
                 info[MISCREG_HYP_RD] = v;
                 return *this;

diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index ebe72dd52eb19bbf34f73b09298912a5fff2dbdb..1eee78116ef97f5df0ac9ded8aa17ffe69edbef4 100644 (file)
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -3165,7 +3165,10 @@ ISA::initializeMiscRegMetadata()
       .bankedChild()
       .secure().exceptUserMode();
     InitReg(MISCREG_MVBAR)
-      .mon().secure().exceptUserMode();
+      .mon().secure()
+      .hypRead(FullSystem && system->highestEL() == EL2)
+      .privRead(FullSystem && system->highestEL() == EL1)
+      .exceptUserMode();
     InitReg(MISCREG_RMR)
       .unimplemented()
       .mon().secure().exceptUserMode();