Fix new tests

diff --git a/tests/arch/xilinx/dsp_cascade.ys b/tests/arch/xilinx/dsp_cascade.ys
index f9185551b2d163d4aaa347b83d2a27535a150c85..ca6b619b91529c35e984f5192a2c09a846f0f709 100644 (file)
--- a/tests/arch/xilinx/dsp_cascade.ys
+++ b/tests/arch/xilinx/dsp_cascade.ys
@@ -19,7 +19,7 @@ EOT
 proc
 design -save read
 
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad
 design -load postopt
 cd cascade
 select -assert-count 3 t:DSP48E1
@@ -35,7 +35,7 @@ select -assert-none t:DSP48E1 t:BUFG %% t:* %D
 select -assert-count 2 t:DSP48E1 %co:+[PCOUT] t:DSP48E1 %d %co:+[PCIN] w:* %d t:DSP48E1 %i
 
 design -load read
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s -noiopad
 design -load postopt
 cd cascade
 select -assert-count 3 t:DSP48A1
@@ -65,7 +65,7 @@ EOT
 proc
 design -save read
 
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad
 design -load postopt
 cd cascade
 select -assert-count 2 t:DSP48E1
@@ -75,7 +75,7 @@ select -assert-none t:DSP48E1 t:BUFG %% t:* %D
 select -assert-count 1 t:DSP48E1 %co:+[PCOUT] t:DSP48E1 %d %co:+[PCIN] w:* %d t:DSP48E1 %i
 
 design -load read
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s -noiopad
 design -load postopt
 cd cascade
 select -assert-count 2 t:DSP48A1

diff --git a/tests/arch/xilinx/mul.ys b/tests/arch/xilinx/mul.ys
index 049a3da7e616b7d3477206bafeba35c8c61185fa..490846ff1a621e9c44722ceda7ee0bafa27413ec 100644 (file)
--- a/tests/arch/xilinx/mul.ys
+++ b/tests/arch/xilinx/mul.ys
@@ -13,7 +13,7 @@ design -reset
 read_verilog ../common/mul.v
 hierarchy -top top
 proc
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s # equivalency check
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 

diff --git a/tests/arch/xilinx/mul_unsigned.ys b/tests/arch/xilinx/mul_unsigned.ys
index 830dd639c38898646c6a9ac21c493673f8044bbd..980263cbd13c518225d113ca9dcbcac48e6eba93 100644 (file)
--- a/tests/arch/xilinx/mul_unsigned.ys
+++ b/tests/arch/xilinx/mul_unsigned.ys
@@ -16,7 +16,7 @@ read_verilog mul_unsigned.v
 hierarchy -top mul_unsigned
 proc
 
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s # equivalency check
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mul_unsigned # Constrain all select calls below inside the top module
 select -assert-count 1 t:BUFG