Fix comments

diff --git a/tests/ice40/add_sub.ys b/tests/ice40/add_sub.ys
index 8eeb221dbf7c34beaf09d253ead5816e1c43afd8..4a998d98d3098ea2ad159b7bccddbfc110edb827 100644 (file)
--- a/tests/ice40/add_sub.ys
+++ b/tests/ice40/add_sub.ys
@@ -1,6 +1,6 @@
 read_verilog add_sub.v
 hierarchy -top top
-equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 11 t:SB_LUT4

diff --git a/tests/ice40/adffs.ys b/tests/ice40/adffs.ys
index 3c676e5908334d1ff37c3782836d72399d7ce98c..14b251c5c5de762372ed15cfbfe42b719750787c 100644 (file)
--- a/tests/ice40/adffs.ys
+++ b/tests/ice40/adffs.ys
@@ -1,8 +1,8 @@
 read_verilog adffs.v
 proc
-async2sync
+async2sync # converts async flops to a 'sync' variant clocked by a 'super'-clock
 flatten
-equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 1 t:SB_DFF

diff --git a/tests/ice40/dffs.ys b/tests/ice40/dffs.ys
index b14346f5a47a1274107c6c99d93a9995cf95a591..ee7f884b1dfc2ae11bb92a5843acfdce03d46e3b 100644 (file)
--- a/tests/ice40/dffs.ys
+++ b/tests/ice40/dffs.ys
@@ -2,7 +2,7 @@ read_verilog dffs.v
 hierarchy -top top
 proc
 flatten
-equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 1 t:SB_DFF

diff --git a/tests/ice40/div_mod.ys b/tests/ice40/div_mod.ys
index 613cad760cc0d412922b1286c506621855167627..96753b4efed2a15a137c040bfdd5ba0c9574bf59 100644 (file)
--- a/tests/ice40/div_mod.ys
+++ b/tests/ice40/div_mod.ys
@@ -1,7 +1,7 @@
 read_verilog div_mod.v
 hierarchy -top top
 flatten
-equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 88 t:SB_LUT4

diff --git a/tests/ice40/memory.ys b/tests/ice40/memory.ys
index 0a8c48dcaeec5c8ed7589534c1e4454cbf20af50..fa5d004b05686a546f7f54326f3890c97d2236ee 100644 (file)
--- a/tests/ice40/memory.ys
+++ b/tests/ice40/memory.ys
@@ -2,4 +2,5 @@ read_verilog memory.v
 synth_ice40
 cd top
 select -assert-count 1 t:SB_RAM40_4K
+select -assert-none t:SB_RAM40_4K %% t:* %D
 write_verilog memory_synth.v

diff --git a/tests/ice40/mul.ys b/tests/ice40/mul.ys
index aec7d0b1fa23ce604cc10a1c1e91707de5181399..8a0822a84024a86d23597f834d23e8322fd6f758 100644 (file)
--- a/tests/ice40/mul.ys
+++ b/tests/ice40/mul.ys
@@ -1,6 +1,6 @@
 read_verilog mul.v
 hierarchy -top top
-equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check same as technology-dependent fine-grained synthesis
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 1 t:SB_MAC16

diff --git a/tests/ice40/mux.ys b/tests/ice40/mux.ys
index 63d22001f1da1e5e2cbbee39901755ae18d9d8d5..182b49499e80bf836a5c4966043a7b7f43509591 100644 (file)
--- a/tests/ice40/mux.ys
+++ b/tests/ice40/mux.ys
@@ -1,8 +1,8 @@
 read_verilog mux.v
 proc
 flatten
-equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40
-design -load postopt
-cd top
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
 select -assert-count 19 t:SB_LUT4
 select -assert-none t:SB_LUT4 %% t:* %D

diff --git a/tests/ice40/tribuf.ys b/tests/ice40/tribuf.ys
index 8049a37abd64f56f9743f4078bfbb08c41a130a1..ef426695926b73c20e00b0bb6b36c80ee25a5daf 100644 (file)
--- a/tests/ice40/tribuf.ys
+++ b/tests/ice40/tribuf.ys
@@ -2,7 +2,7 @@ read_verilog tribuf.v
 hierarchy -top top
 proc
 flatten
-equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 1 t:$_TBUF_