int count_ports = 0;
log("Generating test bench for module `%s'.\n", it->first.c_str());
- for (auto it2 = mod->wires.begin(); it2 != mod->wires.end(); it2++) {
+ for (auto it2 = mod->wires_.begin(); it2 != mod->wires_.end(); it2++) {
RTLIL::Wire *wire = it2->second;
if (wire->port_output) {
count_ports++;
}
}
fprintf(f, "%s %s(\n", id(mod->name).c_str(), idy("uut", mod->name).c_str());
- for (auto it2 = mod->wires.begin(); it2 != mod->wires.end(); it2++) {
+ for (auto it2 = mod->wires_.begin(); it2 != mod->wires_.end(); it2++) {
RTLIL::Wire *wire = it2->second;
if (wire->port_output || wire->port_input)
fprintf(f, "\t.%s(%s)%s\n", id(wire->name).c_str(),
std::map<int, RTLIL::Wire*> inputs, outputs;
- for (auto &wire_it : module->wires) {
+ for (auto &wire_it : module->wires_) {
RTLIL::Wire *wire = wire_it.second;
if (wire->port_input)
inputs[wire->port_id] = wire;
{
line_num=0;
str.clear();
- for(auto it=module->wires.begin(); it!=module->wires.end(); ++it)
+ for(auto it=module->wires_.begin(); it!=module->wires_.end(); ++it)
{
if(it->second->port_input)
{
std::map<int, RTLIL::Wire*> inputs, outputs;
std::vector<RTLIL::Wire*> safety;
- for (auto &wire_it : module->wires) {
+ for (auto &wire_it : module->wires_) {
RTLIL::Wire *wire = wire_it.second;
if (wire->port_input)
inputs[wire->port_id] = wire;
fprintf(f, " (view VIEW_NETLIST\n");
fprintf(f, " (viewType NETLIST)\n");
fprintf(f, " (interface\n");
- for (auto &wire_it : module->wires) {
+ for (auto &wire_it : module->wires_) {
RTLIL::Wire *wire = wire_it.second;
if (wire->port_id == 0)
continue;
if (print_body)
{
- for (auto it = module->wires.begin(); it != module->wires.end(); it++)
+ for (auto it = module->wires_.begin(); it != module->wires_.end(); it++)
if (!only_selected || design->selected(module, it->second)) {
if (only_selected)
fprintf(f, "\n");
netlists_code += stringf("netlist %s\n", RTLIL::id2cstr(module->name));
// Module Ports: "std::set<string> celltypes_code" prevents duplicate top level ports
- for (auto wire_it : module->wires) {
+ for (auto wire_it : module->wires_) {
RTLIL::Wire *wire = wire_it.second;
if (wire->port_input || wire->port_output) {
celltypes_code.insert(stringf("celltype !%s b%d %sPORT\n" "%s %s %d %s PORT\n",
RTLIL::Module *mod = design->modules.at(cell->type);
std::vector<RTLIL::Wire*> ports;
- for (auto wire_it : mod->wires) {
+ for (auto wire_it : mod->wires_) {
RTLIL::Wire *wire = wire_it.second;
if (wire->port_id == 0)
continue;
}
std::vector<RTLIL::Wire*> ports;
- for (auto wire_it : module->wires) {
+ for (auto wire_it : module->wires_) {
RTLIL::Wire *wire = wire_it.second;
if (wire->port_id == 0)
continue;
reset_auto_counter_id(module->name, false);
- for (auto it = module->wires.begin(); it != module->wires.end(); it++)
+ for (auto it = module->wires_.begin(); it != module->wires_.end(); it++)
reset_auto_counter_id(it->second->name, true);
for (auto it = module->cells.begin(); it != module->cells.end(); it++) {
reg_bits.insert(std::pair<RTLIL::Wire*,int>(chunk.wire, chunk.offset+i));
}
}
- for (auto &it : module->wires)
+ for (auto &it : module->wires_)
{
RTLIL::Wire *wire = it.second;
for (int i = 0; i < wire->width; i++)
bool keep_running = true;
for (int port_id = 1; keep_running; port_id++) {
keep_running = false;
- for (auto it = module->wires.begin(); it != module->wires.end(); it++) {
+ for (auto it = module->wires_.begin(); it != module->wires_.end(); it++) {
RTLIL::Wire *wire = it->second;
if (wire->port_id == port_id) {
if (port_id != 1)
}
fprintf(f, ");\n");
- for (auto it = module->wires.begin(); it != module->wires.end(); it++)
+ for (auto it = module->wires_.begin(); it != module->wires_.end(); it++)
dump_wire(f, indent + " ", it->second);
for (auto it = module->memories.begin(); it != module->memories.end(); it++)
chunk.wire->name.c_str(), chunk.width+chunk.offset-1, chunk.offset);;
if (chunk.wire->name.find('$') != std::string::npos)
wire_name += stringf("$%d", RTLIL::autoidx++);
- } while (current_module->wires.count(wire_name) > 0);
+ } while (current_module->wires_.count(wire_name) > 0);
RTLIL::Wire *wire = current_module->addWire(wire_name, chunk.width);
wire->attributes["\\src"] = stringf("%s:%d", always->filename.c_str(), always->linenum);
// create an RTLIL::Wire for an AST_WIRE node
case AST_WIRE: {
- if (current_module->wires.count(str) != 0)
+ if (current_module->wires_.count(str) != 0)
log_error("Re-definition of signal `%s' at %s:%d!\n",
str.c_str(), filename.c_str(), linenum);
if (!range_valid)
RTLIL::Wire *wire = NULL;
RTLIL::SigChunk chunk;
- if (id2ast && id2ast->type == AST_AUTOWIRE && current_module->wires.count(str) == 0) {
+ if (id2ast && id2ast->type == AST_AUTOWIRE && current_module->wires_.count(str) == 0) {
RTLIL::Wire *wire = current_module->addWire(str);
wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
wire->name = str;
goto use_const_chunk;
}
else if (!id2ast || (id2ast->type != AST_WIRE && id2ast->type != AST_AUTOWIRE &&
- id2ast->type != AST_MEMORY) || current_module->wires.count(str) == 0)
+ id2ast->type != AST_MEMORY) || current_module->wires_.count(str) == 0)
log_error("Identifier `%s' doesn't map to any signal at %s:%d!\n",
str.c_str(), filename.c_str(), linenum);
log_error("Identifier `%s' does map to an unexpanded memory at %s:%d!\n",
str.c_str(), filename.c_str(), linenum);
- wire = current_module->wires[str];
+ wire = current_module->wires_[str];
chunk.wire = wire;
chunk.width = wire->width;
chunk.offset = 0;
return *(expr++) == '0' ? RTLIL::State::S0 : RTLIL::State::S1;
std::string id = RTLIL::escape_id(std::string(expr, id_len));
- if (!module->wires.count(id))
+ if (!module->wires_.count(id))
log_error("Can't resolve wire name %s.\n", RTLIL::id2cstr(id));
expr += id_len;
- return module->wires.at(id);
+ return module->wires_.at(id);
}
static RTLIL::SigSpec create_inv_cell(RTLIL::Module *module, RTLIL::SigSpec A)
if (flag_lib && dir->value == "internal")
continue;
- RTLIL::Wire *wire = module->wires.at(RTLIL::escape_id(node->args.at(0)));
+ RTLIL::Wire *wire = module->wires_.at(RTLIL::escape_id(node->args.at(0)));
if (dir && dir->value == "inout") {
wire->port_input = true;
if (cell_types.count(type) == 0) {
for (auto design : designs)
if (design->modules.count(type) > 0) {
- if (design->modules.at(type)->wires.count(port))
- return design->modules.at(type)->wires.at(port)->port_output;
+ if (design->modules.at(type)->wires_.count(port))
+ return design->modules.at(type)->wires_.at(port)->port_output;
return false;
}
return false;
if (cell_types.count(type) == 0) {
for (auto design : designs)
if (design->modules.count(type) > 0) {
- if (design->modules.at(type)->wires.count(port))
- return design->modules.at(type)->wires.at(port)->port_input;
+ if (design->modules.at(type)->wires_.count(port))
+ return design->modules.at(type)->wires_.at(port)->port_input;
return false;
}
return false;
{
RTLIL::Module *module = design->modules.at(design->selected_active_module);
- for (auto &it : module->wires)
+ for (auto &it : module->wires_)
if (RTLIL::unescape_id(it.first).substr(0, len) == text)
obj_names.push_back(strdup(RTLIL::id2cstr(it.first.c_str())));
signal_inputs.clear();
signal_outputs.clear();
- for (auto &it : module->wires)
+ for (auto &it : module->wires_)
add_wire(it.second);
for (auto &it : module->cells)
if (filter_ct == NULL || filter_ct->cell_known(it.second->type))
for (auto &it : selected_members)
if (it.second.size() == 0)
del_list.push_back(it.first);
- else if (it.second.size() == design->modules[it.first]->wires.size() + design->modules[it.first]->memories.size() +
+ else if (it.second.size() == design->modules[it.first]->wires_.size() + design->modules[it.first]->memories.size() +
design->modules[it.first]->cells.size() + design->modules[it.first]->processes.size())
add_list.push_back(it.first);
for (auto mod_name : del_list)
RTLIL::Module::~Module()
{
- for (auto it = wires.begin(); it != wires.end(); it++)
+ for (auto it = wires_.begin(); it != wires_.end(); it++)
delete it->second;
for (auto it = memories.begin(); it != memories.end(); it++)
delete it->second;
size_t RTLIL::Module::count_id(RTLIL::IdString id)
{
- return wires.count(id) + memories.count(id) + cells.count(id) + processes.count(id);
+ return wires_.count(id) + memories.count(id) + cells.count(id) + processes.count(id);
}
#ifndef NDEBUG
void RTLIL::Module::check()
{
#ifndef NDEBUG
- for (auto &it : wires) {
+ for (auto &it : wires_) {
assert(it.first == it.second->name);
assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
assert(it.second->width >= 0);
new_mod->connections_ = connections_;
new_mod->attributes = attributes;
- for (auto &it : wires)
+ for (auto &it : wires_)
new_mod->addWire(it.first, it.second);
for (auto &it : memories)
std::vector<RTLIL::SigChunk> chunks = sig.chunks();
for (auto &c : chunks)
if (c.wire != NULL)
- c.wire = mod->wires.at(c.wire->name);
+ c.wire = mod->wires_.at(c.wire->name);
sig = chunks;
}
};
{
assert(!wire->name.empty());
assert(count_id(wire->name) == 0);
- wires[wire->name] = wire;
+ wires_[wire->name] = wire;
}
void RTLIL::Module::add(RTLIL::Cell *cell)
#if 0
void RTLIL::Module::remove(RTLIL::Wire *wire)
{
- std::set<RTLIL::Wire*> wires;
- wires.insert(wire);
- remove(wires);
+ std::set<RTLIL::Wire*> wires_;
+ wires_.insert(wire);
+ remove(wires_);
}
#endif
rewrite_sigspecs(delete_wire_worker);
for (auto &it : wires) {
- this->wires.erase(it->name);
+ this->wires_.erase(it->name);
delete it;
}
}
void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
{
- assert(wires[wire->name] == wire);
- wires.erase(wire->name);
+ assert(wires_[wire->name] == wire);
+ wires_.erase(wire->name);
wire->name = new_name;
add(wire);
}
void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
{
assert(count_id(old_name) != 0);
- if (wires.count(old_name))
- rename(wires.at(old_name), new_name);
+ if (wires_.count(old_name))
+ rename(wires_.at(old_name), new_name);
else if (cells.count(old_name))
rename(cells.at(old_name), new_name);
else
{
std::vector<RTLIL::Wire*> all_ports;
- for (auto &w : wires)
+ for (auto &w : wires_)
if (w.second->port_input || w.second->port_output)
all_ports.push_back(w.second);
else
if (netname[0] != '$' && netname[0] != '\\')
netname = "\\" + netname;
- if (module->wires.count(netname) == 0) {
+ if (module->wires_.count(netname) == 0) {
size_t indices_pos = netname.size()-1;
if (indices_pos > 2 && netname[indices_pos] == ']')
{
}
}
- if (module->wires.count(netname) == 0)
+ if (module->wires_.count(netname) == 0)
return false;
- RTLIL::Wire *wire = module->wires.at(netname);
+ RTLIL::Wire *wire = module->wires_.at(netname);
if (!indices.empty()) {
std::vector<std::string> index_tokens;
sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
sig = RTLIL::SigSpec();
RTLIL::Selection &sel = design->selection_vars.at(str);
- for (auto &it : module->wires)
+ for (auto &it : module->wires_)
if (sel.selected_member(module->name, it.first))
sig.append(it.second);
public:
RTLIL::IdString name;
std::set<RTLIL::IdString> avail_parameters;
- std::map<RTLIL::IdString, RTLIL::Wire*> wires;
+ std::map<RTLIL::IdString, RTLIL::Wire*> wires_;
std::map<RTLIL::IdString, RTLIL::Memory*> memories;
std::map<RTLIL::IdString, RTLIL::Cell*> cells;
std::map<RTLIL::IdString, RTLIL::Process*> processes;
}
// for each wire in the module
- for (auto &wire_iter : module->wires)
+ for (auto &wire_iter : module->wires_)
{
RTLIL::Wire *wire = wire_iter.second;
log("Modules in current design:\n");
for (auto &mod : design->modules)
log(" %s (%zd wires, %zd cells)\n", RTLIL::id2cstr(mod.first),
- mod.second->wires.size(), mod.second->cells.size());
+ mod.second->wires_.size(), mod.second->cells.size());
}
} MyPass;
RTLIL::Module *module = design->modules.at("\\test");
- RTLIL::SigSpec a(module->wires.at("\\a")), x(module->wires.at("\\x")),
- y(module->wires.at("\\y"));
+ RTLIL::SigSpec a(module->wires_.at("\\a")), x(module->wires_.at("\\x")),
+ y(module->wires_.at("\\y"));
log("%d %d %d\n", a == x, x == y, y == a); // will print "0 0 0"
SigMap sigmap(module);
clk_polarity = false;
clk_str = clk_str.substr(1);
}
- if (module->wires.count(RTLIL::escape_id(clk_str)) != 0)
- clk_sig = assign_map(RTLIL::SigSpec(module->wires.at(RTLIL::escape_id(clk_str)), 0));
+ if (module->wires_.count(RTLIL::escape_id(clk_str)) != 0)
+ clk_sig = assign_map(RTLIL::SigSpec(module->wires_.at(RTLIL::escape_id(clk_str)), 0));
}
if (dff_mode && clk_sig.size() == 0)
for (auto c : cells)
extract_cell(c, keepff);
- for (auto &wire_it : module->wires) {
+ for (auto &wire_it : module->wires_) {
if (wire_it.second->port_id > 0 || wire_it.second->get_bool_attribute("\\keep"))
mark_port(RTLIL::SigSpec(wire_it.second));
}
RTLIL::Module *mapped_mod = mapped_design->modules["\\netlist"];
if (mapped_mod == NULL)
log_error("ABC output file does not contain a module `netlist'.\n");
- for (auto &it : mapped_mod->wires) {
+ for (auto &it : mapped_mod->wires_) {
RTLIL::Wire *w = it.second;
RTLIL::Wire *wire = module->addWire(remap_name(w->name));
design->select(module, wire);
cell_stats[RTLIL::unescape_id(c->type)]++;
if (c->type == "\\ZERO" || c->type == "\\ONE") {
RTLIL::SigSig conn;
- conn.first = RTLIL::SigSpec(module->wires[remap_name(c->get("\\Y").as_wire()->name)]);
+ conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->get("\\Y").as_wire()->name)]);
conn.second = RTLIL::SigSpec(c->type == "\\ZERO" ? 0 : 1, 1);
module->connect(conn);
continue;
}
if (c->type == "\\BUF") {
RTLIL::SigSig conn;
- conn.first = RTLIL::SigSpec(module->wires[remap_name(c->get("\\Y").as_wire()->name)]);
- conn.second = RTLIL::SigSpec(module->wires[remap_name(c->get("\\A").as_wire()->name)]);
+ conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->get("\\Y").as_wire()->name)]);
+ conn.second = RTLIL::SigSpec(module->wires_[remap_name(c->get("\\A").as_wire()->name)]);
module->connect(conn);
continue;
}
if (c->type == "\\INV") {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_INV_");
- cell->set("\\A", RTLIL::SigSpec(module->wires[remap_name(c->get("\\A").as_wire()->name)]));
- cell->set("\\Y", RTLIL::SigSpec(module->wires[remap_name(c->get("\\Y").as_wire()->name)]));
+ cell->set("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\A").as_wire()->name)]));
+ cell->set("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\Y").as_wire()->name)]));
design->select(module, cell);
continue;
}
if (c->type == "\\AND" || c->type == "\\OR" || c->type == "\\XOR") {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_" + c->type.substr(1) + "_");
- cell->set("\\A", RTLIL::SigSpec(module->wires[remap_name(c->get("\\A").as_wire()->name)]));
- cell->set("\\B", RTLIL::SigSpec(module->wires[remap_name(c->get("\\B").as_wire()->name)]));
- cell->set("\\Y", RTLIL::SigSpec(module->wires[remap_name(c->get("\\Y").as_wire()->name)]));
+ cell->set("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\A").as_wire()->name)]));
+ cell->set("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\B").as_wire()->name)]));
+ cell->set("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\Y").as_wire()->name)]));
design->select(module, cell);
continue;
}
if (c->type == "\\MUX") {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_MUX_");
- cell->set("\\A", RTLIL::SigSpec(module->wires[remap_name(c->get("\\A").as_wire()->name)]));
- cell->set("\\B", RTLIL::SigSpec(module->wires[remap_name(c->get("\\B").as_wire()->name)]));
- cell->set("\\S", RTLIL::SigSpec(module->wires[remap_name(c->get("\\S").as_wire()->name)]));
- cell->set("\\Y", RTLIL::SigSpec(module->wires[remap_name(c->get("\\Y").as_wire()->name)]));
+ cell->set("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\A").as_wire()->name)]));
+ cell->set("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\B").as_wire()->name)]));
+ cell->set("\\S", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\S").as_wire()->name)]));
+ cell->set("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\Y").as_wire()->name)]));
design->select(module, cell);
continue;
}
if (c->type == "\\DFF") {
log_assert(clk_sig.size() == 1);
RTLIL::Cell *cell = module->addCell(remap_name(c->name), clk_polarity ? "$_DFF_P_" : "$_DFF_N_");
- cell->set("\\D", RTLIL::SigSpec(module->wires[remap_name(c->get("\\D").as_wire()->name)]));
- cell->set("\\Q", RTLIL::SigSpec(module->wires[remap_name(c->get("\\Q").as_wire()->name)]));
+ cell->set("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\D").as_wire()->name)]));
+ cell->set("\\Q", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\Q").as_wire()->name)]));
cell->set("\\C", clk_sig);
design->select(module, cell);
continue;
cell_stats[RTLIL::unescape_id(c->type)]++;
if (c->type == "\\_const0_" || c->type == "\\_const1_") {
RTLIL::SigSig conn;
- conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections().begin()->second.as_wire()->name)]);
+ conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->connections().begin()->second.as_wire()->name)]);
conn.second = RTLIL::SigSpec(c->type == "\\_const0_" ? 0 : 1, 1);
module->connect(conn);
continue;
if (c->type == "\\_dff_") {
log_assert(clk_sig.size() == 1);
RTLIL::Cell *cell = module->addCell(remap_name(c->name), clk_polarity ? "$_DFF_P_" : "$_DFF_N_");
- cell->set("\\D", RTLIL::SigSpec(module->wires[remap_name(c->get("\\D").as_wire()->name)]));
- cell->set("\\Q", RTLIL::SigSpec(module->wires[remap_name(c->get("\\Q").as_wire()->name)]));
+ cell->set("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\D").as_wire()->name)]));
+ cell->set("\\Q", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\Q").as_wire()->name)]));
cell->set("\\C", clk_sig);
design->select(module, cell);
continue;
if (c.width == 0)
continue;
assert(c.width == 1);
- newsig.append(module->wires[remap_name(c.wire->name)]);
+ newsig.append(module->wires_[remap_name(c.wire->name)]);
}
cell->set(conn.first, newsig);
}
for (auto conn : mapped_mod->connections()) {
if (!conn.first.is_fully_const())
- conn.first = RTLIL::SigSpec(module->wires[remap_name(conn.first.as_wire()->name)]);
+ conn.first = RTLIL::SigSpec(module->wires_[remap_name(conn.first.as_wire()->name)]);
if (!conn.second.is_fully_const())
- conn.second = RTLIL::SigSpec(module->wires[remap_name(conn.second.as_wire()->name)]);
+ conn.second = RTLIL::SigSpec(module->wires_[remap_name(conn.second.as_wire()->name)]);
module->connect(conn);
}
RTLIL::SigSig conn;
if (si.type >= 0) {
conn.first = si.bit;
- conn.second = RTLIL::SigSpec(module->wires[remap_name(buffer)]);
+ conn.second = RTLIL::SigSpec(module->wires_[remap_name(buffer)]);
out_wires++;
} else {
- conn.first = RTLIL::SigSpec(module->wires[remap_name(buffer)]);
+ conn.first = RTLIL::SigSpec(module->wires_[remap_name(buffer)]);
conn.second = si.bit;
in_wires++;
}
char *d = strtok(NULL, " \t\r\n");
char *q = strtok(NULL, " \t\r\n");
- if (module->wires.count(RTLIL::escape_id(d)) == 0)
+ if (module->wires_.count(RTLIL::escape_id(d)) == 0)
module->addWire(RTLIL::escape_id(d));
- if (module->wires.count(RTLIL::escape_id(q)) == 0)
+ if (module->wires_.count(RTLIL::escape_id(q)) == 0)
module->addWire(RTLIL::escape_id(q));
RTLIL::Cell *cell = module->addCell(NEW_ID, dff_name);
- cell->set("\\D", module->wires.at(RTLIL::escape_id(d)));
- cell->set("\\Q", module->wires.at(RTLIL::escape_id(q)));
+ cell->set("\\D", module->wires_.at(RTLIL::escape_id(d)));
+ cell->set("\\Q", module->wires_.at(RTLIL::escape_id(q)));
continue;
}
if (q == NULL || !q[0] || !q[1])
goto error;
*(q++) = 0;
- if (module->wires.count(RTLIL::escape_id(q)) == 0)
+ if (module->wires_.count(RTLIL::escape_id(q)) == 0)
module->addWire(RTLIL::escape_id(q));
- cell->set(RTLIL::escape_id(p), module->wires.at(RTLIL::escape_id(q)));
+ cell->set(RTLIL::escape_id(p), module->wires_.at(RTLIL::escape_id(q)));
}
continue;
}
RTLIL::SigSpec input_sig, output_sig;
while ((p = strtok(NULL, " \t\r\n")) != NULL) {
RTLIL::Wire *wire;
- if (module->wires.count(stringf("\\%s", p)) > 0) {
- wire = module->wires.at(stringf("\\%s", p));
+ if (module->wires_.count(stringf("\\%s", p)) > 0) {
+ wire = module->wires_.at(stringf("\\%s", p));
} else {
wire = module->addWire(stringf("\\%s", p));
}
if (module->count_id(name) != 0)
{
- if (module->wires.count(name) > 0)
- wire = module->wires.at(name);
+ if (module->wires_.count(name) > 0)
+ wire = module->wires_.at(name);
if (wire != NULL && wire->width != width)
wire = NULL;
wire->port_output = flag_output;
if (flag_input || flag_output) {
- wire->port_id = module->wires.size();
+ wire->port_id = module->wires_.size();
module->fixup_ports();
}
RTLIL::Module *module = mod_it.second;
if (flag_input || flag_output) {
- for (auto &it : module->wires)
+ for (auto &it : module->wires_)
if (design->selected(module, it.second)) {
if (flag_input)
it.second->port_input = false;
std::set<std::string> delete_procs;
std::set<std::string> delete_mems;
- for (auto &it : module->wires)
+ for (auto &it : module->wires_)
if (design->selected(module, it.second))
delete_wires.insert(it.second);
if (module->count_id(to_name))
log_cmd_error("There is already an object `%s' in module `%s'.\n", to_name.c_str(), module->name.c_str());
- for (auto &it : module->wires)
+ for (auto &it : module->wires_)
if (it.first == from_name) {
log("Renaming wire %s to %s in module %s.\n", log_id(it.second), log_id(to_name), log_id(module));
module->rename(it.second, to_name);
continue;
std::map<RTLIL::IdString, RTLIL::Wire*> new_wires;
- for (auto &it : module->wires) {
+ for (auto &it : module->wires_) {
if (it.first[0] == '$' && design->selected(module, it.second))
do it.second->name = stringf("\\_%d_", counter++);
while (module->count_id(it.second->name) > 0);
new_wires[it.second->name] = it.second;
}
- module->wires.swap(new_wires);
+ module->wires_.swap(new_wires);
std::map<RTLIL::IdString, RTLIL::Cell*> new_cells;
for (auto &it : module->cells) {
continue;
std::map<RTLIL::IdString, RTLIL::Wire*> new_wires;
- for (auto &it : module->wires) {
+ for (auto &it : module->wires_) {
if (design->selected(module, it.second))
if (it.first[0] == '\\' && it.second->port_id == 0)
it.second->name = NEW_ID;
new_wires[it.second->name] = it.second;
}
- module->wires.swap(new_wires);
+ module->wires_.swap(new_wires);
std::map<RTLIL::IdString, RTLIL::Cell*> new_cells;
for (auto &it : module->cells) {
SigPool selectedSignals;
SigSet<RTLIL::Cell*> sigToNextCells;
- for (auto &it : module->wires)
+ for (auto &it : module->wires_)
if (design->selected(module, it.second))
selectedSignals.add(sigmap(RTLIL::SigSpec(it.second)));
}
RTLIL::Module *mod = mod_it.second;
- for (auto &it : mod->wires)
+ for (auto &it : mod->wires_)
if (!lhs.selected_member(mod_it.first, it.first))
new_sel.selected_members[mod->name].insert(it.first);
for (auto &it : mod->memories)
SigMap sigmap(mod_it.second);
SigPool selected_bits;
- for (auto &it : mod_it.second->wires)
+ for (auto &it : mod_it.second->wires_)
if (lhs.selected_member(mod_it.first, it.first))
selected_bits.add(sigmap(it.second));
- for (auto &it : mod_it.second->wires)
+ for (auto &it : mod_it.second->wires_)
if (!lhs.selected_member(mod_it.first, it.first) && selected_bits.check_any(sigmap(it.second)))
lhs.selected_members[mod_it.first].insert(it.first);
}
if (lhs.selected_modules.count(mod->name) > 0)
{
- for (auto &it : mod->wires)
+ for (auto &it : mod->wires_)
lhs.selected_members[mod->name].insert(it.first);
for (auto &it : mod->memories)
lhs.selected_members[mod->name].insert(it.first);
RTLIL::Module *mod = mod_it.second;
std::set<RTLIL::Wire*> selected_wires;
- for (auto &it : mod->wires)
+ for (auto &it : mod->wires_)
if (lhs.selected_member(mod_it.first, it.first) && limits.count(it.first) == 0)
selected_wires.insert(it.second);
RTLIL::Module *mod = mod_it.second;
if (arg_memb.substr(0, 2) == "w:") {
- for (auto &it : mod->wires)
+ for (auto &it : mod->wires_)
if (match_ids(it.first, arg_memb.substr(2)))
sel.selected_members[mod->name].insert(it.first);
} else
if (arg_memb.substr(0, 2) == "i:") {
- for (auto &it : mod->wires)
+ for (auto &it : mod->wires_)
if (it.second->port_input && match_ids(it.first, arg_memb.substr(2)))
sel.selected_members[mod->name].insert(it.first);
} else
if (arg_memb.substr(0, 2) == "o:") {
- for (auto &it : mod->wires)
+ for (auto &it : mod->wires_)
if (it.second->port_output && match_ids(it.first, arg_memb.substr(2)))
sel.selected_members[mod->name].insert(it.first);
} else
if (arg_memb.substr(0, 2) == "x:") {
- for (auto &it : mod->wires)
+ for (auto &it : mod->wires_)
if ((it.second->port_input || it.second->port_output) && match_ids(it.first, arg_memb.substr(2)))
sel.selected_members[mod->name].insert(it.first);
} else
size_t delim = arg_memb.substr(2).find(':');
if (delim == std::string::npos) {
int width = atoi(arg_memb.substr(2).c_str());
- for (auto &it : mod->wires)
+ for (auto &it : mod->wires_)
if (it.second->width == width)
sel.selected_members[mod->name].insert(it.first);
} else {
std::string max_str = arg_memb.substr(2+delim+1);
int min_width = min_str.empty() ? 0 : atoi(min_str.c_str());
int max_width = max_str.empty() ? -1 : atoi(max_str.c_str());
- for (auto &it : mod->wires)
+ for (auto &it : mod->wires_)
if (min_width <= it.second->width && (it.second->width <= max_width || max_width == -1))
sel.selected_members[mod->name].insert(it.first);
}
sel.selected_members[mod->name].insert(it.first);
} else
if (arg_memb.substr(0, 2) == "a:") {
- for (auto &it : mod->wires)
+ for (auto &it : mod->wires_)
if (match_attr(it.second->attributes, arg_memb.substr(2)))
sel.selected_members[mod->name].insert(it.first);
for (auto &it : mod->memories)
} else {
if (arg_memb.substr(0, 2) == "n:")
arg_memb = arg_memb.substr(2);
- for (auto &it : mod->wires)
+ for (auto &it : mod->wires_)
if (match_ids(it.first, arg_memb))
sel.selected_members[mod->name].insert(it.first);
for (auto &it : mod->memories)
if (sel->selected_whole_module(mod_it.first) && list_mode)
log("%s\n", id2cstr(mod_it.first));
if (sel->selected_module(mod_it.first)) {
- for (auto &it : mod_it.second->wires)
+ for (auto &it : mod_it.second->wires_)
if (sel->selected_member(mod_it.first, it.first))
LOG_OBJECT("%s/%s\n", id2cstr(mod_it.first), id2cstr(it.first));
for (auto &it : mod_it.second->memories)
sel->optimize(design);
for (auto mod_it : design->modules)
if (sel->selected_module(mod_it.first)) {
- for (auto &it : mod_it.second->wires)
+ for (auto &it : mod_it.second->wires_)
if (sel->selected_member(mod_it.first, it.first))
total_count++;
for (auto &it : mod_it.second->memories)
if (design->modules.count(design->selected_active_module) > 0)
{
RTLIL::Module *module = design->modules.at(design->selected_active_module);
- counter += log_matches("wires", pattern, module->wires);
+ counter += log_matches("wires", pattern, module->wires_);
counter += log_matches("memories", pattern, module->memories);
counter += log_matches("cells", pattern, module->cells);
counter += log_matches("processes", pattern, module->processes);
if (!design->selected(module))
continue;
- for (auto &it : module->wires)
+ for (auto &it : module->wires_)
if (design->selected(module, it.second))
do_setunset(it.second->attributes, setunset_list);
SigMap sigmap(module);
SigPool undriven_signals;
- for (auto &it : module->wires)
+ for (auto &it : module->wires_)
if (!it.second->port_input)
undriven_signals.add(sigmap(it.second));
std::set<std::string> all_sources, all_sinks;
std::map<std::string, std::string> wires_on_demand;
- for (auto &it : module->wires) {
+ for (auto &it : module->wires_) {
if (!design->selected_member(module->name, it.first))
continue;
const char *shape = "diamond";
driven_bits.push_back(RTLIL::State::Sm);
driven_bits.push_back(RTLIL::State::Sm);
- for (auto &it : module->wires)
+ for (auto &it : module->wires_)
if (it.second->port_input) {
RTLIL::SigSpec sig = sigmap(it.second);
driven_chunks.insert(sig);
SigPool selected_bits;
if (!sel_by_cell)
- for (auto &it : module->wires)
+ for (auto &it : module->wires_)
if (design->selected(module, it.second))
selected_bits.add(sigmap(it.second));
std::vector<std::pair<RTLIL::Wire*, RTLIL::SigSpec>> rework_wires;
- for (auto &it : module->wires)
+ for (auto &it : module->wires_)
if (!no_outputs && it.second->port_output) {
if (!design->selected(module, it.second))
continue;
}
else
{
- for (auto &w : module->wires) {
+ for (auto &w : module->wires_) {
RTLIL::Wire *wire = w.second;
if (wire->width > 1 && (wire->port_id == 0 || flag_ports) && design->selected(module, w.second))
worker.splitmap[wire] = std::vector<RTLIL::SigBit>();
STAT_INT_MEMBERS
#undef X
- for (auto &it : mod->wires)
+ for (auto &it : mod->wires_)
{
if (!design->selected(mod, it.second))
continue;
}
}
- for (auto &wire_it : module->wires)
+ for (auto &wire_it : module->wires_)
if (wire_it.second->port_id != 0)
sig_at_port.add(assign_map(RTLIL::SigSpec(wire_it.second)));
- for (auto &wire_it : module->wires)
+ for (auto &wire_it : module->wires_)
if (design->selected(module, wire_it.second))
detect_fsm(wire_it.second);
}
// rename original state wire
- module->wires.erase(wire->name);
+ module->wires_.erase(wire->name);
wire->attributes.erase("\\fsm_encoding");
wire->name = stringf("$fsm$oldstate%s", wire->name.c_str());
- module->wires[wire->name] = wire;
+ module->wires_[wire->name] = wire;
// unconnect control outputs from old drivers
}
std::vector<RTLIL::Wire*> wire_list;
- for (auto &wire_it : module->wires)
+ for (auto &wire_it : module->wires_)
if (wire_it.second->attributes.count("\\fsm_encoding") > 0 && wire_it.second->attributes["\\fsm_encoding"].decode_string() != "none")
if (design->selected(module, wire_it.second))
wire_list.push_back(wire_it.second);
std::string portname = conn.first;
if (portname.substr(0, 1) == "$") {
int port_id = atoi(portname.substr(1).c_str());
- for (auto &wire_it : mod->wires)
+ for (auto &wire_it : mod->wires_)
if (wire_it.second->port_id == port_id) {
portname = wire_it.first;
break;
}
}
- if (mod->wires.count(portname) == 0)
+ if (mod->wires_.count(portname) == 0)
log_error("Array cell `%s.%s' connects to unkown port `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(conn.first));
- int port_size = mod->wires.at(portname)->width;
+ int port_size = mod->wires_.at(portname)->width;
if (conn_size == port_size)
continue;
if (conn_size != port_size*num)
}
for (auto module : pos_mods)
- for (auto &wire_it : module->wires) {
+ for (auto &wire_it : module->wires_) {
RTLIL::Wire *wire = wire_it.second;
if (wire->port_id > 0)
pos_map[std::pair<RTLIL::Module*,int>(module, wire->port_id)] = wire->name;
if (opt_name.empty())
{
- for (auto &it : module->wires)
+ for (auto &it : module->wires_)
it.second->attributes.erase("\\submod");
for (auto &it : module->cells)
c->set("\\D", data_reg_in.back());
std::string w_out_name = stringf("%s[%d]", cell->parameters["\\MEMID"].decode_string().c_str(), i);
- if (module->wires.count(w_out_name) > 0)
+ if (module->wires_.count(w_out_name) > 0)
w_out_name = genid(cell->name, "", i, "$q");
RTLIL::Wire *w_out = module->addWire(w_out_name, mem_width);
std::map<RTLIL::SigBit, std::set<RTLIL::SigBit>> muxtree_upstream_map;
std::set<RTLIL::SigBit> non_feedback_nets;
- for (auto wire_it : module->wires)
+ for (auto wire_it : module->wires_)
if (wire_it.second->port_output) {
std::vector<RTLIL::SigBit> bits = RTLIL::SigSpec(wire_it.second);
non_feedback_nets.insert(bits.begin(), bits.end());
unused.insert(cell);
}
- for (auto &it : module->wires) {
+ for (auto &it : module->wires_) {
RTLIL::Wire *wire = it.second;
if (wire->port_output || wire->get_bool_attribute("\\keep")) {
std::set<RTLIL::Cell*> cell_list;
if (ct_all.cell_output(cell->type, it2.first))
direct_sigs.insert(assign_map(it2.second));
}
- for (auto &it : module->wires) {
+ for (auto &it : module->wires_) {
if (direct_sigs.count(assign_map(it.second)) || it.second->port_input)
direct_wires.insert(it.second);
}
- for (auto &it : module->wires) {
+ for (auto &it : module->wires_) {
RTLIL::Wire *wire = it.second;
for (int i = 0; i < wire->width; i++) {
RTLIL::SigBit s1 = RTLIL::SigBit(wire, i), s2 = assign_map(s1);
used_signals_nodrivers.add(it2.second);
}
}
- for (auto &it : module->wires) {
+ for (auto &it : module->wires_) {
RTLIL::Wire *wire = it.second;
if (wire->port_id > 0) {
RTLIL::SigSpec sig = RTLIL::SigSpec(wire);
}
std::vector<RTLIL::Wire*> maybe_del_wires;
- for (auto &it : module->wires) {
+ for (auto &it : module->wires_) {
RTLIL::Wire *wire = it.second;
if ((!purge_mode && check_public_name(wire->name)) || wire->port_id != 0 || wire->get_bool_attribute("\\keep")) {
RTLIL::SigSpec s1 = RTLIL::SigSpec(wire), s2 = s1;
used_signals.add(sigmap(conn.second));
}
- for (auto &it : module->wires) {
+ for (auto &it : module->wires_) {
if (it.second->port_input)
driven_signals.add(sigmap(it.second));
if (it.second->port_output)
}
}
}
- for (auto &it : module->wires) {
+ for (auto &it : module->wires_) {
if (it.second->port_output)
for (int idx : sig2bits(RTLIL::SigSpec(it.second)))
bit2info[idx].seen_non_mux = true;
assign_map.set(mod_it.second);
dff_init_map.set(mod_it.second);
- for (auto &it : mod_it.second->wires)
+ for (auto &it : mod_it.second->wires_)
if (it.second->attributes.count("\\init") != 0)
dff_init_map.add(it.second, it.second->attributes.at("\\init"));
mux_drivers.clear();
assign_map.set(module);
dff_init_map.set(module);
- for (auto &it : module->wires)
+ for (auto &it : module->wires_)
if (it.second->attributes.count("\\init") != 0)
dff_init_map.add(it.second, it.second->attributes.at("\\init"));
if (!design->selected(mod_it.second, proc_it.second))
continue;
proc_arst(mod_it.second, proc_it.second, assign_map);
- if (global_arst.empty() || mod_it.second->wires.count(global_arst) == 0)
+ if (global_arst.empty() || mod_it.second->wires_.count(global_arst) == 0)
continue;
std::vector<RTLIL::SigSig> arst_actions;
for (auto sync : proc_it.second->syncs)
if (!arst_actions.empty()) {
RTLIL::SyncRule *sync = new RTLIL::SyncRule;
sync->type = global_arst_neg ? RTLIL::SyncType::ST0 : RTLIL::SyncType::ST1;
- sync->signal = mod_it.second->wires.at(global_arst);
+ sync->signal = mod_it.second->wires_.at(global_arst);
sync->actions = arst_actions;
proc_it.second->syncs.push_back(sync);
}
mod1(mod1), mod2(mod2), counter(0), errors(0), ignore_x_mod1(ignore_x_mod1)
{
log("Checking for equivialence (brute-force): %s vs %s\n", mod1->name.c_str(), mod2->name.c_str());
- for (auto &w : mod1->wires)
+ for (auto &w : mod1->wires_)
{
RTLIL::Wire *wire1 = w.second;
if (wire1->port_id == 0)
continue;
- if (mod2->wires.count(wire1->name) == 0)
+ if (mod2->wires_.count(wire1->name) == 0)
log_cmd_error("Port %s in module 1 has no counterpart in module 2!\n", wire1->name.c_str());
- RTLIL::Wire *wire2 = mod2->wires.at(wire1->name);
+ RTLIL::Wire *wire2 = mod2->wires_.at(wire1->name);
if (wire1->width != wire2->width || wire1->port_input != wire2->port_input || wire1->port_output != wire2->port_output)
log_cmd_error("Port %s in module 1 does not match its counterpart in module 2!\n", wire1->name.c_str());
ez.assume(satgen.signals_eq(recorded_set_vars, recorded_set_vals));
- std::vector<int> y_vec = satgen.importDefSigSpec(module->wires.at("\\y"));
+ std::vector<int> y_vec = satgen.importDefSigSpec(module->wires_.at("\\y"));
std::vector<bool> y_values;
if (model_undef) {
- std::vector<int> y_undef_vec = satgen.importUndefSigSpec(module->wires.at("\\y"));
+ std::vector<int> y_undef_vec = satgen.importUndefSigSpec(module->wires_.at("\\y"));
y_vec.insert(y_vec.end(), y_undef_vec.begin(), y_undef_vec.end());
}
std::vector<RTLIL::State> bits(patterns[idx].bits.begin(), patterns[idx].bits.begin() + total_input_width);
for (int i = 0; i < int(inputs.size()); i++) {
- RTLIL::Wire *wire = module->wires.at(inputs[i]);
+ RTLIL::Wire *wire = module->wires_.at(inputs[i]);
for (int j = input_widths[i]-1; j >= 0; j--) {
ce.set(RTLIL::SigSpec(wire, j), bits.back());
recorded_set_vars.append(RTLIL::SigSpec(wire, j));
}
}
- if (module->wires.count("\\y") == 0)
+ if (module->wires_.count("\\y") == 0)
log_error("No output wire (y) found in module %s!\n", RTLIL::id2cstr(module->name));
- RTLIL::SigSpec sig(module->wires.at("\\y"));
+ RTLIL::SigSpec sig(module->wires_.at("\\y"));
RTLIL::SigSpec undef;
while (!ce.eval(sig, undef)) {
int width = -1;
RTLIL::IdString esc_name = RTLIL::escape_id(name);
for (auto mod : modules) {
- if (mod->wires.count(esc_name) == 0)
+ if (mod->wires_.count(esc_name) == 0)
log_error("Can't find input %s in module %s!\n", name.c_str(), RTLIL::id2cstr(mod->name));
- RTLIL::Wire *port = mod->wires.at(esc_name);
+ RTLIL::Wire *port = mod->wires_.at(esc_name);
if (!port->port_input || port->port_output)
log_error("Wire %s in module %s is not an input!\n", name.c_str(), RTLIL::id2cstr(mod->name));
if (width >= 0 && width != port->width)
}
if (shows.size() == 0) {
- for (auto &it : module->wires)
+ for (auto &it : module->wires_)
if (it.second->port_output)
shows.push_back(it.second->name);
}
dffsignals.add(sigmap(it.second->get("\\Q")));
}
- for (auto &it : module->wires) {
+ for (auto &it : module->wires_) {
if (dffsignals.check_any(it.second))
dff_wires.insert(it.first);
}
}
std::map<std::string, dff_map_info_t> empty_dq_map;
- for (auto &it : module->wires)
+ for (auto &it : module->wires_)
{
if (!consider_wire(it.second, empty_dq_map))
continue;
for (auto &it : shared_dff_wires) {
if (!dff_dq_maps[mod_it.second].count(it))
continue;
- if (!compare_wires(first_module->wires.at(it), mod_it.second->wires.at(it)))
+ if (!compare_wires(first_module->wires_.at(it), mod_it.second->wires_.at(it)))
continue;
new_shared_dff_wires.insert(it);
}
if (first_module == NULL)
{
- for (auto &it : module->wires)
+ for (auto &it : module->wires_)
if (design->selected(module, it.second) && consider_wire(it.second, dff_dq_maps[module]))
if (!flag_dff || dff_wires.count(it.first))
shared_wires.insert(it.first);
{
RTLIL::Wire *wire;
- if (module->wires.count(it) == 0)
+ if (module->wires_.count(it) == 0)
goto delete_shared_wire;
- wire = module->wires.at(it);
+ wire = module->wires_.at(it);
if (!design->selected(module, wire))
goto delete_shared_wire;
if (!consider_wire(wire, dff_dq_maps[module]))
goto delete_shared_wire;
- if (!compare_wires(first_module->wires.at(it), wire))
+ if (!compare_wires(first_module->wires_.at(it), wire))
goto delete_shared_wire;
if (flag_dff && !dff_wires.count(it))
goto delete_shared_wire;
SigMap out_to_in_map;
- for (auto &it : module->wires)
+ for (auto &it : module->wires_)
{
if (flag_shared) {
if (shared_wires.count(it.first) == 0)
for (auto &dq : dff_dq_maps[module])
{
- if (!module->wires.count(dq.first))
+ if (!module->wires_.count(dq.first))
continue;
- RTLIL::Wire *wire = module->wires.at(dq.first);
+ RTLIL::Wire *wire = module->wires_.at(dq.first);
std::set<RTLIL::SigBit> wire_bits_set = sigmap(wire).to_sigbit_set();
std::vector<RTLIL::SigBit> wire_bits_vec = sigmap(wire).to_sigbit_vector();
{
RTLIL::Module *mod = design->modules.at(cell->type);
- for (auto &it : mod->wires)
+ for (auto &it : mod->wires_)
{
RTLIL::Wire *p = it.second;
if (!p->port_input && !p->port_output)
int bits_full_total = 0;
std::vector<std::set<RTLIL::SigBit>> batches;
- for (auto &it : module->wires)
+ for (auto &it : module->wires_)
if (it.second->port_input) {
batches.push_back(sigmap(it.second).to_sigbit_set());
bits_full_total += it.second->width;
RTLIL::Module *gold_module = design->modules.at(gold_name);
RTLIL::Module *gate_module = design->modules.at(gate_name);
- for (auto &it : gold_module->wires) {
+ for (auto &it : gold_module->wires_) {
RTLIL::Wire *w1 = it.second, *w2;
if (w1->port_id == 0)
continue;
- if (gate_module->wires.count(it.second->name) == 0)
+ if (gate_module->wires_.count(it.second->name) == 0)
goto match_gold_port_error;
- w2 = gate_module->wires.at(it.second->name);
+ w2 = gate_module->wires_.at(it.second->name);
if (w1->port_input != w2->port_input)
goto match_gold_port_error;
if (w1->port_output != w2->port_output)
log_cmd_error("No matching port in gate module was found for %s!\n", it.second->name.c_str());
}
- for (auto &it : gate_module->wires) {
+ for (auto &it : gate_module->wires_) {
RTLIL::Wire *w1 = it.second, *w2;
if (w1->port_id == 0)
continue;
- if (gold_module->wires.count(it.second->name) == 0)
+ if (gold_module->wires_.count(it.second->name) == 0)
goto match_gate_port_error;
- w2 = gold_module->wires.at(it.second->name);
+ w2 = gold_module->wires_.at(it.second->name);
if (w1->port_input != w2->port_input)
goto match_gate_port_error;
if (w1->port_output != w2->port_output)
RTLIL::SigSpec all_conditions;
- for (auto &it : gold_module->wires)
+ for (auto &it : gold_module->wires_)
{
RTLIL::Wire *w1 = it.second;
RTLIL::SigSpec big_lhs, big_rhs;
- for (auto &it : module->wires)
+ for (auto &it : module->wires_)
{
if (it.second->attributes.count("\\init") == 0)
continue;
log_cmd_error("The options -set-init-undef, -set-init-def, and -set-init-zero are exclusive!\n");
if (set_def_inputs) {
- for (auto &it : module->wires)
+ for (auto &it : module->wires_)
if (it.second->port_input)
sets_def.push_back(it.second->name);
}
if (show_inputs) {
- for (auto &it : module->wires)
+ for (auto &it : module->wires_)
if (it.second->port_input)
shows.push_back(it.second->name);
}
if (show_outputs) {
- for (auto &it : module->wires)
+ for (auto &it : module->wires_)
if (it.second->port_output)
shows.push_back(it.second->name);
}
}
// mark external signals (used in module ports)
- for (auto &wire_it : mod->wires)
+ for (auto &wire_it : mod->wires_)
{
RTLIL::Wire *wire = wire_it.second;
if (wire->port_id > 0)
RTLIL::Cell *cell = haystack->addCell(stringf("$extract$%s$%d", needle->name.c_str(), RTLIL::autoidx++), needle->name);
// create cell ports
- for (auto &it : needle->wires) {
+ for (auto &it : needle->wires_) {
RTLIL::Wire *wire = it.second;
if (wire->port_id > 0) {
for (int i = 0; i < wire->width; i++)
std::vector<RTLIL::SigChunk> chunks = sigmap(conn.second);
for (auto &chunk : chunks)
if (chunk.wire != NULL)
- chunk.wire = newMod->wires.at(chunk.wire->name);
+ chunk.wire = newMod->wires_.at(chunk.wire->name);
newCell->set(conn.first, chunks);
}
}
if (!design->selected(module) || module->get_bool_attribute("\\blackbox"))
continue;
- for (auto &it2 : module->wires)
+ for (auto &it2 : module->wires_)
{
RTLIL::Wire *wire = it2.second;
if (chunk.wire != NULL) {
std::string wire_name = chunk.wire->name;
apply_prefix(prefix, wire_name);
- assert(module->wires.count(wire_name) > 0);
- chunk.wire = module->wires[wire_name];
+ assert(module->wires_.count(wire_name) > 0);
+ chunk.wire = module->wires_[wire_name];
}
sig = chunks;
}
if (module == NULL)
return result;
- for (auto &it : module->wires) {
+ for (auto &it : module->wires_) {
const char *p = it.first.c_str();
if (*p == '$')
continue;
std::map<RTLIL::IdString, RTLIL::IdString> positional_ports;
- for (auto &it : tpl->wires) {
+ for (auto &it : tpl->wires_) {
if (it.second->port_id > 0)
positional_ports[stringf("$%d", it.second->port_id)] = it.first;
std::string w_name = it.second->name;
RTLIL::IdString portname = it.first;
if (positional_ports.count(portname) > 0)
portname = positional_ports.at(portname);
- if (tpl->wires.count(portname) == 0 || tpl->wires.at(portname)->port_id == 0) {
+ if (tpl->wires_.count(portname) == 0 || tpl->wires_.at(portname)->port_id == 0) {
if (portname.substr(0, 1) == "$")
log_error("Can't map port `%s' of cell `%s' to template `%s'!\n", portname.c_str(), cell->name.c_str(), tpl->name.c_str());
continue;
}
- RTLIL::Wire *w = tpl->wires.at(portname);
+ RTLIL::Wire *w = tpl->wires_.at(portname);
RTLIL::SigSig c;
if (w->port_output) {
c.first = it.second;
for (auto conn : cell->connections()) {
if (conn.first.substr(0, 1) == "$")
continue;
- if (tpl->wires.count(conn.first) > 0 && tpl->wires.at(conn.first)->port_id > 0)
+ if (tpl->wires_.count(conn.first) > 0 && tpl->wires_.at(conn.first)->port_id > 0)
continue;
if (!conn.second.is_fully_const() || parameters.count(conn.first) > 0 || tpl->avail_parameters.count(conn.first) == 0)
goto next_tpl;
assert(!strncmp(q, "_TECHMAP_DO_", 12));
std::string new_name = data.wire->name.substr(0, q-p) + "_TECHMAP_DONE_" + data.wire->name.substr(q-p+12);
- while (tpl->wires.count(new_name))
+ while (tpl->wires_.count(new_name))
new_name += "_";
tpl->rename(data.wire, new_name);
projects / yosys.git / commitdiff