i965/gen6: Fix GPU hang when using stencil buffer without depth

Enable the bit 3DSTATE_DEPTH_BUFFER.Tiled_Surface.  From the Sandybridge
PRM, Volume 2, Part 1, Section 7.5.5.1.1 3DSTATE_DEPTH_BUFFER, Bit 1.27
Tiled Surface:
   [DevGT+]: This field must be set to TRUE.

Fixes GPU hangs on the following Piglit tests:
   hiz-stencil-test-fbo-d0-s8
   hiz-stencil-read-fbo-d0-s8

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>

diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 17da46099ed15ee6b0d4d9a7397c3f2a902694d9..cb1405ca8664c045523bd3e9578c9e46cec1f8b9 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -278,6 +278,10 @@ static void emit_depthbuffer(struct brw_context *brw)
        *
        *     [DevGT]: This field must be set to the same value (enabled or
        *     disabled) as Hierarchical Depth Buffer Enable
+       *
+       * The tiled bit must be set. From the Sandybridge PRM, Volume 2, Part 1,
+       * Section 7.5.5.1.1 3DSTATE_DEPTH_BUFFER, Bit 1.27 Tiled Surface:
+       *     [DevGT+]: This field must be set to TRUE.
        */
       struct intel_region *region = stencil_irb->mt->region;
 
@@ -290,6 +294,7 @@ static void emit_depthbuffer(struct brw_context *brw)
                (1 << 21) | /* separate stencil enable */
                (1 << 22) | /* hiz enable */
                (BRW_TILEWALK_YMAJOR << 26) |
+               (1 << 27) | /* tiled surface */
                (BRW_SURFACE_2D << 29));
       OUT_BATCH(0);
       OUT_BATCH(((region->width - 1) << 6) |