kernel/version_$(GIT_REV).cc: Makefile
$(P) rm -f kernel/version_*.o kernel/version_*.d kernel/version_*.cc
- $(Q) echo "extern const char *yosys_version_str; const char *yosys_version_str=\"Yosys $(YOSYS_VER) (git sha1 $(GIT_REV), $(CXX) ` \
- $(CXX) --version | tr ' ()' '\n' | grep '^[0-9]' | head -n1` $(filter -f% -m% -O% -DNDEBUG,$(CXXFLAGS)))\";" > kernel/version_$(GIT_REV).cc
+ $(Q) echo "namespace Yosys { extern const char *yosys_version_str; const char *yosys_version_str=\"Yosys $(YOSYS_VER) (git sha1 $(GIT_REV), $(CXX) ` \
+ $(CXX) --version | tr ' ()' '\n' | grep '^[0-9]' | head -n1` $(filter -f% -m% -O% -DNDEBUG,$(CXXFLAGS)))\"; }" > kernel/version_$(GIT_REV).cc
yosys-config: yosys-config.in
$(P) $(SED) -e 's,@CXX@,$(CXX),;' -e 's,@CXXFLAGS@,$(CXXFLAGS),;' -e 's,@LDFLAGS@,$(LDFLAGS),;' -e 's,@LDLIBS@,$(LDLIBS),;' \
#include "kernel/log.h"
#include <string>
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
struct BlifDumperConfig
{
bool icells_mode;
}
} BlifBackend;
+PRIVATE_NAMESPACE_END
#include <string>
#include <math.h>
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
struct BtorDumperConfig
{
bool subckt_mode;
}
} BtorBackend;
+PRIVATE_NAMESPACE_END
#include "kernel/log.h"
#include <string>
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
#define EDIF_DEF(_id) edif_names(RTLIL::unescape_id(_id), true).c_str()
#define EDIF_REF(_id) edif_names(RTLIL::unescape_id(_id), false).c_str()
}
} EdifBackend;
+PRIVATE_NAMESPACE_END
#include "kernel/yosys.h"
#include <errno.h>
+USING_YOSYS_NAMESPACE
using namespace ILANG_BACKEND;
+YOSYS_NAMESPACE_BEGIN
void ILANG_BACKEND::dump_const(std::ostream &f, const RTLIL::Const &data, int width, int offset, bool autoint)
{
log_assert(init_autoidx == autoidx);
}
+YOSYS_NAMESPACE_END
+PRIVATE_NAMESPACE_BEGIN
+
struct IlangBackend : public Backend {
IlangBackend() : Backend("ilang", "write design to ilang file") { }
virtual void help()
}
} DumpPass;
+PRIVATE_NAMESPACE_END
#include "kernel/log.h"
#include <string>
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
static std::string netname(std::set<std::string> &conntypes_code, std::set<std::string> &celltypes_code, std::set<std::string> &constcells_code, RTLIL::SigSpec sig)
{
}
} IntersynthBackend;
+PRIVATE_NAMESPACE_END
#include "kernel/log.h"
#include <string>
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
static void print_spice_net(std::ostream &f, RTLIL::SigBit s, std::string &neg, std::string &pos, std::string &ncpf, int &nc_counter)
{
if (s.wire) {
}
} SpiceBackend;
+PRIVATE_NAMESPACE_END
*
*/
-#include "verilog_backend.h"
#include "kernel/register.h"
#include "kernel/celltypes.h"
#include "kernel/log.h"
#include <set>
#include <map>
-namespace {
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
bool norename, noattr, attr2comment, noexpr;
int auto_name_counter, auto_name_offset, auto_name_digits;
active_module = NULL;
}
-} /* namespace */
-
struct VerilogBackend : public Backend {
VerilogBackend() : Backend("verilog", "write design to verilog file") { }
virtual void help()
}
} VerilogBackend;
+PRIVATE_NAMESPACE_END
+++ /dev/null
-/*
- * yosys -- Yosys Open SYnthesis Suite
- *
- * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- * ---
- *
- * A simple and straightforward verilog backend.
- *
- * Note that RTLIL processes can't always be mapped easily to a Verilog
- * process. Therefore this frontend should only be used to export a
- * Verilog netlist (i.e. after the "proc" pass has converted all processes
- * to logic networks and registers).
- *
- */
-
-#ifndef VERILOG_BACKEND_H
-#define VERILOG_BACKEND_H
-
-#include "kernel/yosys.h"
-
-namespace VERILOG_BACKEND {
- void verilog_backend(std::ostream &f, std::vector<std::string> args, RTLIL::Design *design);
-}
-
-#endif
#include <dlfcn.h>
#include <ffi.h>
+YOSYS_NAMESPACE_BEGIN
+
typedef void (*ffi_fptr) ();
static ffi_fptr resolve_fn (std::string symbol_name)
return newNode;
}
+YOSYS_NAMESPACE_END
+
#else /* YOSYS_ENABLE_PLUGINS */
+YOSYS_NAMESPACE_BEGIN
+
AST::AstNode *AST::dpi_call(const std::string&, const std::string &fname, const std::vector<std::string>&, const std::vector<AstNode*>&)
{
log_error("Can't call DPI function `%s': this version of yosys is built without plugin support\n", fname.c_str());
}
+YOSYS_NAMESPACE_END
+
#endif /* YOSYS_ENABLE_PLUGINS */
#include "kernel/register.h"
#include "kernel/log.h"
-YOSYS_NAMESPACE_BEGIN
-
void rtlil_frontend_ilang_yyerror(char const *s)
{
- log_error("Parser error in line %d: %s\n", rtlil_frontend_ilang_yyget_lineno(), s);
+ YOSYS_NAMESPACE_PREFIX log_error("Parser error in line %d: %s\n", rtlil_frontend_ilang_yyget_lineno(), s);
}
+YOSYS_NAMESPACE_BEGIN
+
struct IlangFrontend : public Frontend {
IlangFrontend() : Frontend("ilang", "read modules from ilang file") { }
virtual void help()
#include "ilang_frontend.h"
#include "parser.tab.h"
+USING_YOSYS_NAMESPACE
+
#define YY_INPUT(buf,result,max_size) \
result = ILANG_FRONTEND::lexin->readsome(buf, max_size);
#include "kernel/log.h"
YOSYS_NAMESPACE_BEGIN
-using namespace PASS_DFFLIBMAP;
struct token_t {
char type;
}
} VerilogFrontend;
-// the yyerror function used by bison to report parser errors
-void frontend_verilog_yyerror(char const *fmt, ...)
-{
- va_list ap;
- char buffer[1024];
- char *p = buffer;
- p += snprintf(p, buffer + sizeof(buffer) - p, "Parser error in line %s:%d: ",
- AST::current_filename.c_str(), frontend_verilog_yyget_lineno());
- va_start(ap, fmt);
- p += vsnprintf(p, buffer + sizeof(buffer) - p, fmt, ap);
- va_end(ap);
- p += snprintf(p, buffer + sizeof(buffer) - p, "\n");
- log_error("%s", buffer);
- exit(1);
-}
-
struct VerilogDefaults : public Pass {
VerilogDefaults() : Pass("verilog_defaults", "set default options for read_verilog") { }
virtual void help()
YOSYS_NAMESPACE_END
+// the yyerror function used by bison to report parser errors
+void frontend_verilog_yyerror(char const *fmt, ...)
+{
+ va_list ap;
+ char buffer[1024];
+ char *p = buffer;
+ p += snprintf(p, buffer + sizeof(buffer) - p, "Parser error in line %s:%d: ",
+ YOSYS_NAMESPACE_PREFIX AST::current_filename.c_str(), frontend_verilog_yyget_lineno());
+ va_start(ap, fmt);
+ p += vsnprintf(p, buffer + sizeof(buffer) - p, fmt, ap);
+ va_end(ap);
+ p += snprintf(p, buffer + sizeof(buffer) - p, "\n");
+ YOSYS_NAMESPACE_PREFIX log_error("%s", buffer);
+ exit(1);
+}
+
#include "kernel/log.h"
#include "kernel/rtlil.h"
+YOSYS_NAMESPACE_BEGIN
+
struct BitPatternPool
{
int width;
}
};
+YOSYS_NAMESPACE_END
+
#endif
#include "kernel/celltypes.h"
#include "kernel/macc.h"
+YOSYS_NAMESPACE_BEGIN
+
struct ConstEval
{
RTLIL::Module *module;
}
};
+YOSYS_NAMESPACE_END
+
#endif
#include <sys/time.h>
#include <sys/resource.h>
+// from libs/sha1/sha1.h
+class SHA1;
+
YOSYS_NAMESPACE_BEGIN
#define S__LINE__sub2(x) #x
extern std::vector<FILE*> log_files;
extern std::vector<std::ostream*> log_streams;
extern FILE *log_errfile;
-extern class SHA1 *log_hasher;
+extern SHA1 *log_hasher;
extern bool log_time;
extern bool log_cmd_error_throw;
void log_cell(RTLIL::Cell *cell, std::string indent = "");
-#define log_abort() log_error("Abort in %s:%d.\n", __FILE__, __LINE__)
-#define log_assert(_assert_expr_) do { if (_assert_expr_) break; log_error("Assert `%s' failed in %s:%d.\n", #_assert_expr_, __FILE__, __LINE__); } while (0)
-#define log_ping() log("-- %s:%d %s --\n", __FILE__, __LINE__, __PRETTY_FUNCTION__)
+#define log_abort() YOSYS_NAMESPACE_PREFIX log_error("Abort in %s:%d.\n", __FILE__, __LINE__)
+#define log_assert(_assert_expr_) do { if (_assert_expr_) break; YOSYS_NAMESPACE_PREFIX log_error("Assert `%s' failed in %s:%d.\n", #_assert_expr_, __FILE__, __LINE__); } while (0)
+#define log_ping() YOSYS_NAMESPACE_PREFIX log("-- %s:%d %s --\n", __FILE__, __LINE__, __PRETTY_FUNCTION__)
// ---------------------------------------------------
#include "kernel/macc.h"
#include "libs/ezsat/ezminisat.h"
+
+YOSYS_NAMESPACE_BEGIN
+
typedef ezMiniSAT ezDefaultSAT;
struct SatGen
}
};
+YOSYS_NAMESPACE_END
+
#endif
#ifndef UTILS_H
#define UTILS_H
+YOSYS_NAMESPACE_BEGIN
+
// ------------------------------------------------
// A map-like container, but you can save and restore the state
// ------------------------------------------------
}
};
+YOSYS_NAMESPACE_END
+
#endif
#define PRIVATE_NAMESPACE_BEGIN namespace {
#define PRIVATE_NAMESPACE_END }
-
-#if 0
-# define YOSYS_NAMESPACE_BEGIN namespace Yosys {
-# define YOSYS_NAMESPACE_END }
-# define YOSYS_NAMESPACE_PREFIX Yosys::
-# define USING_YOSYS_NAMESPACE using namespace Yosys;
-#else
-# define YOSYS_NAMESPACE_BEGIN
-# define YOSYS_NAMESPACE_END
-# define YOSYS_NAMESPACE_PREFIX
-# define USING_YOSYS_NAMESPACE
-#endif
+#define YOSYS_NAMESPACE_BEGIN namespace Yosys {
+#define YOSYS_NAMESPACE_END }
+#define YOSYS_NAMESPACE_PREFIX Yosys::
+#define USING_YOSYS_NAMESPACE using namespace Yosys;
#if __cplusplus >= 201103L
# define OVERRIDE override
#include "blifparse.h"
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
enum class gate_type_t {
G_NONE,
G_FF,
}
} AbcPass;
+ PRIVATE_NAMESPACE_END
*/
#include "blifparse.h"
-#include "kernel/log.h"
-#include <stdio.h>
-#include <string.h>
+
+YOSYS_NAMESPACE_BEGIN
static bool read_next_line(char *&buffer, size_t &buffer_size, int &line_count, FILE *f)
{
// return NULL;
}
+YOSYS_NAMESPACE_END
+
#ifndef ABC_BLIFPARSE
#define ABC_BLIFPARSE
-#include "kernel/rtlil.h"
+#include "kernel/yosys.h"
+
+YOSYS_NAMESPACE_BEGIN
extern RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name);
-#endif
+YOSYS_NAMESPACE_END
+#endif
*
*/
-#include "kernel/register.h"
-#include "kernel/rtlil.h"
-#include "kernel/log.h"
+#include "kernel/yosys.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string name, int width, bool flag_input, bool flag_output, bool flag_global)
{
}
} AddPass;
+PRIVATE_NAMESPACE_END
#include "kernel/celltypes.h"
#include "kernel/log.h"
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap &sigmap, RTLIL::SigSpec &sig)
{
CellTypes ct(design);
}
} ConnectPass;
+PRIVATE_NAMESPACE_END
#include "kernel/rtlil.h"
#include "kernel/log.h"
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
struct ConnwrappersWorker
{
struct portdecl_t {
}
} ConnwrappersPass;
+PRIVATE_NAMESPACE_END
#include "kernel/rtlil.h"
#include "kernel/log.h"
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
struct CopyPass : public Pass {
CopyPass() : Pass("copy", "copy modules in the design") { }
virtual void help()
}
} CopyPass;
+PRIVATE_NAMESPACE_END
#include "kernel/rtlil.h"
#include "kernel/log.h"
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
struct CoverPass : public Pass {
CoverPass() : Pass("cover", "print code coverage counters") { }
virtual void help()
}
} CoverPass;
+PRIVATE_NAMESPACE_END
*
*/
-#include "kernel/register.h"
-#include "kernel/rtlil.h"
-#include "kernel/log.h"
+#include "kernel/yosys.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
struct DeletePass : public Pass {
DeletePass() : Pass("delete", "delete objects in the design") { }
}
} DeletePass;
+PRIVATE_NAMESPACE_END
#include "kernel/rtlil.h"
#include "kernel/log.h"
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
struct LogPass : public Pass {
LogPass() : Pass("log", "print text and log files") { }
virtual void help()
}
} LogPass;
+PRIVATE_NAMESPACE_END
#include "kernel/rtlil.h"
#include "kernel/log.h"
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
static void rename_in_module(RTLIL::Module *module, std::string from_name, std::string to_name)
{
from_name = RTLIL::escape_id(from_name);
}
} RenamePass;
+PRIVATE_NAMESPACE_END
#include "kernel/rtlil.h"
#include "kernel/log.h"
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
struct ScatterPass : public Pass {
ScatterPass() : Pass("scatter", "add additional intermediate nets") { }
virtual void help()
}
} ScatterPass;
+PRIVATE_NAMESPACE_END
#include <stdio.h>
#include <set>
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
struct SccWorker
{
RTLIL::Design *design;
}
} SccPass;
+PRIVATE_NAMESPACE_END
#include <fnmatch.h>
#include <errno.h>
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
using RTLIL::id2cstr;
static std::vector<RTLIL::Selection> work_stack;
select_filter_active_mod(design, work_stack.back());
}
+PRIVATE_NAMESPACE_END
+YOSYS_NAMESPACE_BEGIN
+
// used in kernel/register.cc and maybe other locations, extern decl. in register.h
void handle_extra_select_args(Pass *pass, std::vector<std::string> args, size_t argidx, size_t args_size, RTLIL::Design *design)
{
design->selection_stack.push_back(RTLIL::Selection(false));
}
+YOSYS_NAMESPACE_END
+PRIVATE_NAMESPACE_BEGIN
+
struct SelectPass : public Pass {
SelectPass() : Pass("select", "modify and view the list of selected objects") { }
virtual void help()
}
} LsPass;
+PRIVATE_NAMESPACE_END
#include "kernel/rtlil.h"
#include "kernel/log.h"
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
struct setunset_t
{
RTLIL::IdString name;
}
} SetparamPass;
+PRIVATE_NAMESPACE_END
#include "kernel/rtlil.h"
#include "kernel/log.h"
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
struct SetundefWorker
{
int next_bit_mode;
}
} SetundefPass;
+PRIVATE_NAMESPACE_END
# include <readline/readline.h>
#endif
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
using RTLIL::id2cstr;
#undef CLUSTER_CELLS_AND_PORTBOXES
}
} ShowPass;
+PRIVATE_NAMESPACE_END
#include "kernel/log.h"
#include <tuple>
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
struct SpliceWorker
{
RTLIL::Design *design;
}
} SplicePass;
+PRIVATE_NAMESPACE_END
#include "kernel/rtlil.h"
#include "kernel/log.h"
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
struct SplitnetsWorker
{
std::map<RTLIL::Wire*, std::vector<RTLIL::SigBit>> splitmap;
}
} SplitnetsPass;
+PRIVATE_NAMESPACE_END
#include "kernel/celltypes.h"
#include "kernel/log.h"
-namespace
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct statdata_t
{
- struct statdata_t
+ #define STAT_INT_MEMBERS X(num_wires) X(num_wire_bits) X(num_pub_wires) X(num_pub_wire_bits) \
+ X(num_memories) X(num_memory_bits) X(num_cells) X(num_processes)
+
+ #define X(_name) int _name;
+ STAT_INT_MEMBERS
+ #undef X
+
+ std::map<RTLIL::IdString, int> num_cells_by_type;
+
+ statdata_t operator+(const statdata_t &other) const
{
- #define STAT_INT_MEMBERS X(num_wires) X(num_wire_bits) X(num_pub_wires) X(num_pub_wire_bits) \
- X(num_memories) X(num_memory_bits) X(num_cells) X(num_processes)
+ statdata_t sum = other;
+ #define X(_name) sum._name += _name;
+ STAT_INT_MEMBERS
+ #undef X
+ for (auto &it : num_cells_by_type)
+ sum.num_cells_by_type[it.first] += it.second;
+ return sum;
+ }
- #define X(_name) int _name;
+ statdata_t operator*(int other) const
+ {
+ statdata_t sum = *this;
+ #define X(_name) sum._name *= other;
STAT_INT_MEMBERS
- #undef X
+ #undef X
+ for (auto &it : sum.num_cells_by_type)
+ it.second *= other;
+ return sum;
+ }
- std::map<RTLIL::IdString, int> num_cells_by_type;
+ statdata_t()
+ {
+ #define X(_name) _name = 0;
+ STAT_INT_MEMBERS
+ #undef X
+ }
- statdata_t operator+(const statdata_t &other) const
- {
- statdata_t sum = other;
- #define X(_name) sum._name += _name;
- STAT_INT_MEMBERS
- #undef X
- for (auto &it : num_cells_by_type)
- sum.num_cells_by_type[it.first] += it.second;
- return sum;
- }
+ statdata_t(RTLIL::Design *design, RTLIL::Module *mod, bool width_mode)
+ {
+ #define X(_name) _name = 0;
+ STAT_INT_MEMBERS
+ #undef X
- statdata_t operator*(int other) const
+ for (auto &it : mod->wires_)
{
- statdata_t sum = *this;
- #define X(_name) sum._name *= other;
- STAT_INT_MEMBERS
- #undef X
- for (auto &it : sum.num_cells_by_type)
- it.second *= other;
- return sum;
+ if (!design->selected(mod, it.second))
+ continue;
+
+ if (it.first[0] == '\\') {
+ num_pub_wires++;
+ num_pub_wire_bits += it.second->width;
+ }
+
+ num_wires++;
+ num_wire_bits += it.second->width;
}
- statdata_t()
- {
- #define X(_name) _name = 0;
- STAT_INT_MEMBERS
- #undef X
+ for (auto &it : mod->memories) {
+ if (!design->selected(mod, it.second))
+ continue;
+ num_memories++;
+ num_memory_bits += it.second->width * it.second->size;
}
- statdata_t(RTLIL::Design *design, RTLIL::Module *mod, bool width_mode)
+ for (auto &it : mod->cells_)
{
- #define X(_name) _name = 0;
- STAT_INT_MEMBERS
- #undef X
-
- for (auto &it : mod->wires_)
- {
- if (!design->selected(mod, it.second))
- continue;
-
- if (it.first[0] == '\\') {
- num_pub_wires++;
- num_pub_wire_bits += it.second->width;
- }
-
- num_wires++;
- num_wire_bits += it.second->width;
- }
+ if (!design->selected(mod, it.second))
+ continue;
- for (auto &it : mod->memories) {
- if (!design->selected(mod, it.second))
- continue;
- num_memories++;
- num_memory_bits += it.second->width * it.second->size;
- }
+ RTLIL::IdString cell_type = it.second->type;
- for (auto &it : mod->cells_)
+ if (width_mode)
{
- if (!design->selected(mod, it.second))
- continue;
-
- RTLIL::IdString cell_type = it.second->type;
-
- if (width_mode)
- {
- if (cell_type.in("$not", "$pos", "$neg",
- "$logic_not", "$logic_and", "$logic_or",
- "$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool",
- "$lut", "$and", "$or", "$xor", "$xnor",
- "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx",
- "$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt",
- "$add", "$sub", "$mul", "$div", "$mod", "$pow")) {
- int width_a = it.second->hasPort("\\A") ? SIZE(it.second->getPort("\\A")) : 0;
- int width_b = it.second->hasPort("\\B") ? SIZE(it.second->getPort("\\B")) : 0;
- int width_y = it.second->hasPort("\\Y") ? SIZE(it.second->getPort("\\Y")) : 0;
- cell_type = stringf("%s_%d", cell_type.c_str(), std::max<int>({width_a, width_b, width_y}));
- }
- else if (cell_type.in("$mux", "$pmux"))
- cell_type = stringf("%s_%d", cell_type.c_str(), SIZE(it.second->getPort("\\Y")));
- else if (cell_type.in("$sr", "$dff", "$dffsr", "$adff", "$dlatch", "$dlatchsr"))
- cell_type = stringf("%s_%d", cell_type.c_str(), SIZE(it.second->getPort("\\Q")));
+ if (cell_type.in("$not", "$pos", "$neg",
+ "$logic_not", "$logic_and", "$logic_or",
+ "$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool",
+ "$lut", "$and", "$or", "$xor", "$xnor",
+ "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx",
+ "$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt",
+ "$add", "$sub", "$mul", "$div", "$mod", "$pow")) {
+ int width_a = it.second->hasPort("\\A") ? SIZE(it.second->getPort("\\A")) : 0;
+ int width_b = it.second->hasPort("\\B") ? SIZE(it.second->getPort("\\B")) : 0;
+ int width_y = it.second->hasPort("\\Y") ? SIZE(it.second->getPort("\\Y")) : 0;
+ cell_type = stringf("%s_%d", cell_type.c_str(), std::max<int>({width_a, width_b, width_y}));
}
-
- num_cells++;
- num_cells_by_type[cell_type]++;
+ else if (cell_type.in("$mux", "$pmux"))
+ cell_type = stringf("%s_%d", cell_type.c_str(), SIZE(it.second->getPort("\\Y")));
+ else if (cell_type.in("$sr", "$dff", "$dffsr", "$adff", "$dlatch", "$dlatchsr"))
+ cell_type = stringf("%s_%d", cell_type.c_str(), SIZE(it.second->getPort("\\Q")));
}
- for (auto &it : mod->processes) {
- if (!design->selected(mod, it.second))
- continue;
- num_processes++;
- }
+ num_cells++;
+ num_cells_by_type[cell_type]++;
}
- void log_data()
- {
- log(" Number of wires: %6d\n", num_wires);
- log(" Number of wire bits: %6d\n", num_wire_bits);
- log(" Number of public wires: %6d\n", num_pub_wires);
- log(" Number of public wire bits: %6d\n", num_pub_wire_bits);
- log(" Number of memories: %6d\n", num_memories);
- log(" Number of memory bits: %6d\n", num_memory_bits);
- log(" Number of processes: %6d\n", num_processes);
- log(" Number of cells: %6d\n", num_cells);
- for (auto &it : num_cells_by_type)
- log(" %-26s %6d\n", RTLIL::id2cstr(it.first), it.second);
+ for (auto &it : mod->processes) {
+ if (!design->selected(mod, it.second))
+ continue;
+ num_processes++;
}
- };
+ }
- statdata_t hierarchy_worker(std::map<RTLIL::IdString, statdata_t> &mod_stat, RTLIL::IdString mod, int level)
+ void log_data()
{
- statdata_t mod_data = mod_stat.at(mod);
- std::map<RTLIL::IdString, int> num_cells_by_type;
- num_cells_by_type.swap(mod_data.num_cells_by_type);
-
+ log(" Number of wires: %6d\n", num_wires);
+ log(" Number of wire bits: %6d\n", num_wire_bits);
+ log(" Number of public wires: %6d\n", num_pub_wires);
+ log(" Number of public wire bits: %6d\n", num_pub_wire_bits);
+ log(" Number of memories: %6d\n", num_memories);
+ log(" Number of memory bits: %6d\n", num_memory_bits);
+ log(" Number of processes: %6d\n", num_processes);
+ log(" Number of cells: %6d\n", num_cells);
for (auto &it : num_cells_by_type)
- if (mod_stat.count(it.first) > 0) {
- log(" %*s%-*s %6d\n", 2*level, "", 26-2*level, RTLIL::id2cstr(it.first), it.second);
- mod_data = mod_data + hierarchy_worker(mod_stat, it.first, level+1) * it.second;
- mod_data.num_cells -= it.second;
- } else {
- mod_data.num_cells_by_type[it.first] += it.second;
- }
-
- return mod_data;
+ log(" %-26s %6d\n", RTLIL::id2cstr(it.first), it.second);
}
+};
+
+statdata_t hierarchy_worker(std::map<RTLIL::IdString, statdata_t> &mod_stat, RTLIL::IdString mod, int level)
+{
+ statdata_t mod_data = mod_stat.at(mod);
+ std::map<RTLIL::IdString, int> num_cells_by_type;
+ num_cells_by_type.swap(mod_data.num_cells_by_type);
+
+ for (auto &it : num_cells_by_type)
+ if (mod_stat.count(it.first) > 0) {
+ log(" %*s%-*s %6d\n", 2*level, "", 26-2*level, RTLIL::id2cstr(it.first), it.second);
+ mod_data = mod_data + hierarchy_worker(mod_stat, it.first, level+1) * it.second;
+ mod_data.num_cells -= it.second;
+ } else {
+ mod_data.num_cells_by_type[it.first] += it.second;
+ }
+
+ return mod_data;
}
struct StatPass : public Pass {
}
} StatPass;
+PRIVATE_NAMESPACE_END
#include "kernel/rtlil.h"
#include "kernel/log.h"
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
struct TeePass : public Pass {
TeePass() : Pass("tee", "redirect command output to file") { }
virtual void help()
}
} TeePass;
+PRIVATE_NAMESPACE_END
#include "kernel/yosys.h"
+USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct TraceMonitor : public RTLIL::Monitor
#include "kernel/yosys.h"
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
struct WriteFileFrontend : public Frontend {
WriteFileFrontend() : Frontend("=write_file", "write a text to a file") { }
virtual void help()
}
} WriteFileFrontend;
+PRIVATE_NAMESPACE_END
#include <stdlib.h>
#include <stdio.h>
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
struct FsmPass : public Pass {
FsmPass() : Pass("fsm", "extract and optimize finite state machines") { }
virtual void help()
}
} FsmPass;
+PRIVATE_NAMESPACE_END
#include "kernel/celltypes.h"
#include "fsmdata.h"
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
static RTLIL::Module *module;
static SigMap assign_map;
typedef std::pair<RTLIL::Cell*, RTLIL::IdString> sig2driver_entry_t;
}
} FsmDetectPass;
+PRIVATE_NAMESPACE_END
#include "fsmdata.h"
#include <string.h>
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
struct FsmExpand
{
RTLIL::Module *module;
}
} FsmExpandPass;
+PRIVATE_NAMESPACE_END
#include <iostream>
#include <fstream>
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
/**
* Convert a signal into a KISS-compatible textual representation.
*/
}
}
} FsmExportPass;
+
+PRIVATE_NAMESPACE_END
#include "kernel/celltypes.h"
#include "fsmdata.h"
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
static RTLIL::Module *module;
static SigMap assign_map;
typedef std::pair<RTLIL::IdString, RTLIL::IdString> sig2driver_entry_t;
}
} FsmExtractPass;
+PRIVATE_NAMESPACE_END
#include "fsmdata.h"
#include <string.h>
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
struct FsmInfoPass : public Pass {
FsmInfoPass() : Pass("fsm_info", "print information on finite state machines") { }
virtual void help()
}
} FsmInfoPass;
+PRIVATE_NAMESPACE_END
#include "fsmdata.h"
#include <string.h>
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
static bool pattern_is_subset(const RTLIL::Const &super_pattern, const RTLIL::Const &sub_pattern)
{
log_assert(SIZE(super_pattern.bits) == SIZE(sub_pattern.bits));
}
} FsmMapPass;
+PRIVATE_NAMESPACE_END
#include "fsmdata.h"
#include <string.h>
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
struct FsmOpt
{
FsmData fsm_data;
}
};
-void FsmData::optimize_fsm(RTLIL::Cell *cell, RTLIL::Module *module)
+PRIVATE_NAMESPACE_END
+
+void YOSYS_NAMESPACE_PREFIX FsmData::optimize_fsm(RTLIL::Cell *cell, RTLIL::Module *module)
{
FsmOpt fsmopt(cell, module);
}
+PRIVATE_NAMESPACE_BEGIN
+
struct FsmOptPass : public Pass {
FsmOptPass() : Pass("fsm_opt", "optimize finite state machines") { }
virtual void help()
}
} FsmOptPass;
+PRIVATE_NAMESPACE_END
#include <string.h>
#include <errno.h>
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
static void fm_set_fsm_print(RTLIL::Cell *cell, RTLIL::Module *module, FsmData &fsm_data, const char *prefix, FILE *f)
{
std::string name = cell->parameters["\\NAME"].decode_string();
}
} FsmRecodePass;
+PRIVATE_NAMESPACE_END
#ifndef FSMDATA_H
#define FSMDATA_H
-#include "kernel/rtlil.h"
-#include "kernel/log.h"
+#include "kernel/yosys.h"
+
+YOSYS_NAMESPACE_BEGIN
struct FsmData
{
static void optimize_fsm(RTLIL::Cell *cell, RTLIL::Module *module);
};
+YOSYS_NAMESPACE_END
+
#endif
#include <set>
#include <unistd.h>
-namespace {
- struct generate_port_decl_t {
- bool input, output;
- RTLIL::IdString portname;
- int index;
- };
-}
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct generate_port_decl_t {
+ bool input, output;
+ RTLIL::IdString portname;
+ int index;
+};
-static void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes, const std::vector<generate_port_decl_t> &portdecls)
+void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes, const std::vector<generate_port_decl_t> &portdecls)
{
std::set<RTLIL::IdString> found_celltypes;
}
}
-static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check, std::vector<std::string> &libdirs)
+bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check, std::vector<std::string> &libdirs)
{
bool did_something = false;
std::map<RTLIL::Cell*, std::pair<int, int>> array_cells;
return did_something;
}
-static void hierarchy_worker(RTLIL::Design *design, std::set<RTLIL::Module*> &used, RTLIL::Module *mod, int indent)
+void hierarchy_worker(RTLIL::Design *design, std::set<RTLIL::Module*> &used, RTLIL::Module *mod, int indent)
{
if (used.count(mod) > 0)
return;
}
}
-static void hierarchy(RTLIL::Design *design, RTLIL::Module *top, bool purge_lib, bool first_pass)
+void hierarchy(RTLIL::Design *design, RTLIL::Module *top, bool purge_lib, bool first_pass)
{
std::set<RTLIL::Module*> used;
hierarchy_worker(design, used, top, 0);
}
} HierarchyPass;
+PRIVATE_NAMESPACE_END
#include <stdio.h>
#include <set>
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
struct SubmodWorker
{
CellTypes ct;
}
} SubmodPass;
+PRIVATE_NAMESPACE_END
#include <stdlib.h>
#include <stdio.h>
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
struct MemoryPass : public Pass {
MemoryPass() : Pass("memory", "translate memories to basic cells") { }
virtual void help()
}
} MemoryPass;
+PRIVATE_NAMESPACE_END
#include <algorithm>
#include <stdlib.h>
-static bool memcells_cmp(RTLIL::Cell *a, RTLIL::Cell *b)
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+bool memcells_cmp(RTLIL::Cell *a, RTLIL::Cell *b)
{
if (a->type == "$memrd" && b->type == "$memrd")
return a->name < b->name;
return a->parameters.at("\\PRIORITY").as_int() < b->parameters.at("\\PRIORITY").as_int();
}
-static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
+void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
{
log("Collecting $memrd and $memwr for memory `%s' in module `%s':\n",
memory->name.c_str(), module->name.c_str());
}
} MemoryCollectPass;
+PRIVATE_NAMESPACE_END
#include <stdlib.h>
#include <sstream>
-static void normalize_sig(RTLIL::Module *module, RTLIL::SigSpec &sig)
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+void normalize_sig(RTLIL::Module *module, RTLIL::SigSpec &sig)
{
for (auto &conn : module->connections())
sig.replace(conn.first, conn.second);
}
-static bool find_sig_before_dff(RTLIL::Module *module, std::vector<RTLIL::Cell*> &dff_cells, RTLIL::SigSpec &sig, RTLIL::SigSpec &clk, bool &clk_polarity, bool after = false)
+bool find_sig_before_dff(RTLIL::Module *module, std::vector<RTLIL::Cell*> &dff_cells, RTLIL::SigSpec &sig, RTLIL::SigSpec &clk, bool &clk_polarity, bool after = false)
{
normalize_sig(module, sig);
return true;
}
-static void handle_wr_cell(RTLIL::Module *module, std::vector<RTLIL::Cell*> &dff_cells, RTLIL::Cell *cell)
+void handle_wr_cell(RTLIL::Module *module, std::vector<RTLIL::Cell*> &dff_cells, RTLIL::Cell *cell)
{
log("Checking cell `%s' in module `%s': ", cell->name.c_str(), module->name.c_str());
log("no (compatible) $dff found.\n");
}
-static void disconnect_dff(RTLIL::Module *module, RTLIL::SigSpec sig)
+void disconnect_dff(RTLIL::Module *module, RTLIL::SigSpec sig)
{
normalize_sig(module, sig);
sig.sort_and_unify();
}
}
-static void handle_rd_cell(RTLIL::Module *module, std::vector<RTLIL::Cell*> &dff_cells, RTLIL::Cell *cell)
+void handle_rd_cell(RTLIL::Module *module, std::vector<RTLIL::Cell*> &dff_cells, RTLIL::Cell *cell)
{
log("Checking cell `%s' in module `%s': ", cell->name.c_str(), module->name.c_str());
log("no (compatible) $dff found.\n");
}
-static void handle_module(RTLIL::Module *module, bool flag_wr_only)
+void handle_module(RTLIL::Module *module, bool flag_wr_only)
{
std::vector<RTLIL::Cell*> dff_cells;
}
} MemoryDffPass;
+PRIVATE_NAMESPACE_END
#include <set>
#include <stdlib.h>
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
struct MemoryMapWorker
{
RTLIL::Design *design;
}
} MemoryMapPass;
+PRIVATE_NAMESPACE_END
#include "kernel/sigtools.h"
#include "kernel/modtools.h"
+USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
-static bool memcells_cmp(RTLIL::Cell *a, RTLIL::Cell *b)
+bool memcells_cmp(RTLIL::Cell *a, RTLIL::Cell *b)
{
if (a->type == "$memrd" && b->type == "$memrd")
return a->name < b->name;
} MemorySharePass;
PRIVATE_NAMESPACE_END
-
#include <algorithm>
#include <stdlib.h>
-static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory)
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory)
{
log("Creating $memrd and $memwr for memory `%s' in module `%s':\n",
memory->name.c_str(), module->name.c_str());
module->remove(memory);
}
-static void handle_module(RTLIL::Design *design, RTLIL::Module *module)
+void handle_module(RTLIL::Design *design, RTLIL::Module *module)
{
std::vector<RTLIL::IdString> memcells;
for (auto &cell_it : module->cells_)
}
} MemoryUnpackPass;
+PRIVATE_NAMESPACE_END
#include <stdlib.h>
#include <stdio.h>
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
struct OptPass : public Pass {
OptPass() : Pass("opt", "perform simple optimizations") { }
virtual void help()
}
} OptPass;
+PRIVATE_NAMESPACE_END
#include <stdio.h>
#include <set>
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
using RTLIL::id2cstr;
-static CellTypes ct, ct_reg, ct_all;
-static int count_rm_cells, count_rm_wires;
+CellTypes ct, ct_reg, ct_all;
+int count_rm_cells, count_rm_wires;
-static void rmunused_module_cells(RTLIL::Module *module, bool verbose)
+void rmunused_module_cells(RTLIL::Module *module, bool verbose)
{
SigMap assign_map(module);
std::set<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> queue, unused;
}
}
-static int count_nontrivial_wire_attrs(RTLIL::Wire *w)
+int count_nontrivial_wire_attrs(RTLIL::Wire *w)
{
int count = w->attributes.size();
count -= w->attributes.count("\\src");
return count;
}
-static bool compare_signals(RTLIL::SigBit &s1, RTLIL::SigBit &s2, SigPool ®s, SigPool &conns, std::set<RTLIL::Wire*> &direct_wires)
+bool compare_signals(RTLIL::SigBit &s1, RTLIL::SigBit &s2, SigPool ®s, SigPool &conns, std::set<RTLIL::Wire*> &direct_wires)
{
RTLIL::Wire *w1 = s1.wire;
RTLIL::Wire *w2 = s2.wire;
return w2->name < w1->name;
}
-static bool check_public_name(RTLIL::IdString id)
+bool check_public_name(RTLIL::IdString id)
{
const std::string &id_str = id.str();
if (id_str[0] == '$')
return true;
}
-static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbose)
+void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbose)
{
SigPool register_signals;
SigPool connected_signals;
log(" removed %d unused temporary wires.\n", del_wires_count);
}
-static void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose)
+void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose)
{
if (verbose)
log("Finding unused cells or wires in module %s..\n", module->name.c_str());
}
} CleanPass;
+PRIVATE_NAMESPACE_END
#include <stdio.h>
#include <algorithm>
-static bool did_something;
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
-static void replace_undriven(RTLIL::Design *design, RTLIL::Module *module)
+bool did_something;
+
+void replace_undriven(RTLIL::Design *design, RTLIL::Module *module)
{
CellTypes ct(design);
SigMap sigmap(module);
}
}
-static void replace_cell(SigMap &assign_map, RTLIL::Module *module, RTLIL::Cell *cell, std::string info, std::string out_port, RTLIL::SigSpec out_val)
+void replace_cell(SigMap &assign_map, RTLIL::Module *module, RTLIL::Cell *cell, std::string info, std::string out_port, RTLIL::SigSpec out_val)
{
RTLIL::SigSpec Y = cell->getPort(out_port);
out_val.extend_u0(Y.size(), false);
did_something = true;
}
-static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutative, SigMap &sigmap)
+bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutative, SigMap &sigmap)
{
std::string b_name = cell->hasPort("\\B") ? "\\B" : "\\A";
return true;
}
-static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool consume_x, bool mux_undef, bool mux_bool, bool do_fine, bool keepdc)
+void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool consume_x, bool mux_undef, bool mux_bool, bool do_fine, bool keepdc)
{
if (!design->selected(module))
return;
}
} OptConstPass;
+PRIVATE_NAMESPACE_END
#include <stdio.h>
#include <set>
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
using RTLIL::id2cstr;
struct OptMuxtreeWorker
}
} OptMuxtreePass;
+PRIVATE_NAMESPACE_END
#include <stdio.h>
#include <set>
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
struct OptReduceWorker
{
RTLIL::Design *design;
}
} OptReducePass;
+PRIVATE_NAMESPACE_END
#include <stdlib.h>
#include <stdio.h>
-static SigMap assign_map, dff_init_map;
-static SigSet<RTLIL::Cell*> mux_drivers;
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
-static bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
+SigMap assign_map, dff_init_map;
+SigSet<RTLIL::Cell*> mux_drivers;
+
+bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
{
RTLIL::SigSpec sig_d, sig_q, sig_c, sig_r;
RTLIL::Const val_cp, val_rp, val_rv;
}
} OptRmdffPass;
+PRIVATE_NAMESPACE_END
#define USE_CELL_HASH_CACHE
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
struct OptShareWorker
{
RTLIL::Design *design;
}
} OptSharePass;
+PRIVATE_NAMESPACE_END
#include "kernel/modtools.h"
#include "kernel/utils.h"
+USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct ShareWorkerConfig
} SharePass;
PRIVATE_NAMESPACE_END
-
#include <stdlib.h>
#include <stdio.h>
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
struct ProcPass : public Pass {
ProcPass() : Pass("proc", "translate processes to netlists") { }
virtual void help()
}
} ProcPass;
+PRIVATE_NAMESPACE_END
#include <stdlib.h>
#include <stdio.h>
-// defined in proc_clean.cc
+YOSYS_NAMESPACE_BEGIN
extern void proc_clean_case(RTLIL::CaseRule *cs, bool &did_something, int &count, int max_depth);
+YOSYS_NAMESPACE_END
-static bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSpec ref, bool &polarity)
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSpec ref, bool &polarity)
{
if (signal.size() != 1)
return false;
return false;
}
-static void apply_const(RTLIL::Module *mod, const RTLIL::SigSpec rspec, RTLIL::SigSpec &rval, RTLIL::CaseRule *cs, RTLIL::SigSpec const_sig, bool polarity, bool unknown)
+void apply_const(RTLIL::Module *mod, const RTLIL::SigSpec rspec, RTLIL::SigSpec &rval, RTLIL::CaseRule *cs, RTLIL::SigSpec const_sig, bool polarity, bool unknown)
{
for (auto &action : cs->actions) {
if (unknown)
}
}
-static void eliminate_const(RTLIL::Module *mod, RTLIL::CaseRule *cs, RTLIL::SigSpec const_sig, bool polarity)
+void eliminate_const(RTLIL::Module *mod, RTLIL::CaseRule *cs, RTLIL::SigSpec const_sig, bool polarity)
{
for (auto sw : cs->switches) {
bool this_polarity = polarity;
}
}
-static void proc_arst(RTLIL::Module *mod, RTLIL::Process *proc, SigMap &assign_map)
+void proc_arst(RTLIL::Module *mod, RTLIL::Process *proc, SigMap &assign_map)
{
restart_proc_arst:
if (proc->root_case.switches.size() != 1)
}
} ProcArstPass;
+PRIVATE_NAMESPACE_END
#include <stdlib.h>
#include <stdio.h>
-extern void proc_clean_switch(RTLIL::SwitchRule *sw, RTLIL::CaseRule *parent, bool &did_something, int &count, int max_depth);
+YOSYS_NAMESPACE_BEGIN
extern void proc_clean_case(RTLIL::CaseRule *cs, bool &did_something, int &count, int max_depth);
+YOSYS_NAMESPACE_END
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
void proc_clean_switch(RTLIL::SwitchRule *sw, RTLIL::CaseRule *parent, bool &did_something, int &count, int max_depth)
{
}
}
+PRIVATE_NAMESPACE_END
+YOSYS_NAMESPACE_BEGIN
+
void proc_clean_case(RTLIL::CaseRule *cs, bool &did_something, int &count, int max_depth)
{
for (size_t i = 0; i < cs->actions.size(); i++) {
}
}
-static void proc_clean(RTLIL::Module *mod, RTLIL::Process *proc, int &total_count)
+YOSYS_NAMESPACE_END
+PRIVATE_NAMESPACE_BEGIN
+
+void proc_clean(RTLIL::Module *mod, RTLIL::Process *proc, int &total_count)
{
int count = 0;
bool did_something = true;
}
} ProcCleanPass;
+PRIVATE_NAMESPACE_END
#include <stdlib.h>
#include <stdio.h>
-static RTLIL::SigSpec find_any_lvalue(const RTLIL::Process *proc)
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+RTLIL::SigSpec find_any_lvalue(const RTLIL::Process *proc)
{
RTLIL::SigSpec lvalue;
return lvalue;
}
-static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, RTLIL::SigSpec clk, bool clk_polarity,
+void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, RTLIL::SigSpec clk, bool clk_polarity,
std::map<RTLIL::SigSpec, std::set<RTLIL::SyncRule*>> &async_rules, RTLIL::Process *proc)
{
RTLIL::SigSpec sig_sr_set = RTLIL::SigSpec(0, sig_d.size());
cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative");
}
-static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_out,
+void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_out,
bool clk_polarity, bool set_polarity, RTLIL::SigSpec clk, RTLIL::SigSpec set, RTLIL::Process *proc)
{
std::stringstream sstr;
clk_polarity ? "positive" : "negative", set_polarity ? "positive" : "negative");
}
-static void gen_dff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::Const val_rst, RTLIL::SigSpec sig_out,
+void gen_dff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::Const val_rst, RTLIL::SigSpec sig_out,
bool clk_polarity, bool arst_polarity, RTLIL::SigSpec clk, RTLIL::SigSpec *arst, RTLIL::Process *proc)
{
std::stringstream sstr;
log(".\n");
}
-static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
+void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
{
while (1)
{
}
} ProcDffPass;
+PRIVATE_NAMESPACE_END
#include <stdlib.h>
#include <stdio.h>
-static void proc_get_const(RTLIL::SigSpec &sig, RTLIL::CaseRule &rule)
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+void proc_get_const(RTLIL::SigSpec &sig, RTLIL::CaseRule &rule)
{
log_assert(rule.compare.size() == 0);
}
}
-static void proc_init(RTLIL::Module *mod, RTLIL::Process *proc)
+void proc_init(RTLIL::Module *mod, RTLIL::Process *proc)
{
bool found_init = false;
}
} ProcInitPass;
+PRIVATE_NAMESPACE_END
#include <stdlib.h>
#include <stdio.h>
-static RTLIL::SigSpec find_any_lvalue(const RTLIL::CaseRule *cs)
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+RTLIL::SigSpec find_any_lvalue(const RTLIL::CaseRule *cs)
{
for (auto &action : cs->actions) {
if (action.first.size())
return RTLIL::SigSpec();
}
-static void extract_core_signal(const RTLIL::CaseRule *cs, RTLIL::SigSpec &sig)
+void extract_core_signal(const RTLIL::CaseRule *cs, RTLIL::SigSpec &sig)
{
for (auto &action : cs->actions) {
RTLIL::SigSpec lvalue = action.first.extract(sig);
extract_core_signal(cs2, sig);
}
-static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SwitchRule *sw)
+RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SwitchRule *sw)
{
std::stringstream sstr;
sstr << "$procmux$" << (autoidx++);
return RTLIL::SigSpec(ctrl_wire);
}
-static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SigSpec when_signal, RTLIL::SigSpec else_signal, RTLIL::Cell *&last_mux_cell, RTLIL::SwitchRule *sw)
+RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SigSpec when_signal, RTLIL::SigSpec else_signal, RTLIL::Cell *&last_mux_cell, RTLIL::SwitchRule *sw)
{
log_assert(when_signal.size() == else_signal.size());
return RTLIL::SigSpec(result_wire);
}
-static void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SigSpec when_signal, RTLIL::Cell *last_mux_cell, RTLIL::SwitchRule *sw)
+void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SigSpec when_signal, RTLIL::Cell *last_mux_cell, RTLIL::SwitchRule *sw)
{
log_assert(last_mux_cell != NULL);
log_assert(when_signal.size() == last_mux_cell->getPort("\\A").size());
last_mux_cell->parameters["\\S_WIDTH"] = last_mux_cell->getPort("\\S").size();
}
-static RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, RTLIL::CaseRule *cs, const RTLIL::SigSpec &sig, const RTLIL::SigSpec &defval)
+RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, RTLIL::CaseRule *cs, const RTLIL::SigSpec &sig, const RTLIL::SigSpec &defval)
{
RTLIL::SigSpec result = defval;
return result;
}
-static void proc_mux(RTLIL::Module *mod, RTLIL::Process *proc)
+void proc_mux(RTLIL::Module *mod, RTLIL::Process *proc)
{
bool first = true;
while (1)
}
} ProcMuxPass;
+PRIVATE_NAMESPACE_END
#include <stdio.h>
#include <set>
-static void proc_rmdead(RTLIL::SwitchRule *sw, int &counter)
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+void proc_rmdead(RTLIL::SwitchRule *sw, int &counter)
{
BitPatternPool pool(sw->signal);
}
} ProcRmdeadPass;
+PRIVATE_NAMESPACE_END
#include <string.h>
#include <algorithm>
-namespace {
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
/* this should only be used for regression testing of ConstEval -- see vloghammer */
struct BruteForceEquivChecker
}
};
-} /* namespace */
-
struct EvalPass : public Pass {
EvalPass() : Pass("eval", "evaluate the circuit given an input") { }
virtual void help()
}
} EvalPass;
+PRIVATE_NAMESPACE_END
#include "kernel/rtlil.h"
#include "kernel/log.h"
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
struct dff_map_info_t {
RTLIL::SigSpec sig_d, sig_clk, sig_arst;
bool clk_polarity, arst_polarity;
RTLIL::Cell *cell;
};
-static bool consider_wire(RTLIL::Wire *wire, std::map<RTLIL::IdString, dff_map_info_t> &dff_dq_map)
+bool consider_wire(RTLIL::Wire *wire, std::map<RTLIL::IdString, dff_map_info_t> &dff_dq_map)
{
if (wire->name[0] == '$' || dff_dq_map.count(wire->name))
return false;
return true;
}
-static bool consider_cell(RTLIL::Design *design, std::set<RTLIL::IdString> &dff_cells, RTLIL::Cell *cell)
+bool consider_cell(RTLIL::Design *design, std::set<RTLIL::IdString> &dff_cells, RTLIL::Cell *cell)
{
if (cell->name[0] == '$' || dff_cells.count(cell->name))
return false;
return true;
}
-static bool compare_wires(RTLIL::Wire *wire1, RTLIL::Wire *wire2)
+bool compare_wires(RTLIL::Wire *wire1, RTLIL::Wire *wire2)
{
log_assert(wire1->name == wire2->name);
if (wire1->width != wire2->width)
return true;
}
-static bool compare_cells(RTLIL::Cell *cell1, RTLIL::Cell *cell2)
+bool compare_cells(RTLIL::Cell *cell1, RTLIL::Cell *cell2)
{
log_assert(cell1->name == cell2->name);
if (cell1->type != cell2->type)
return true;
}
-static void find_dff_wires(std::set<RTLIL::IdString> &dff_wires, RTLIL::Module *module)
+void find_dff_wires(std::set<RTLIL::IdString> &dff_wires, RTLIL::Module *module)
{
CellTypes ct;
ct.setup_internals_mem();
}
}
-static void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::Design *design, RTLIL::Module *module)
+void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::Design *design, RTLIL::Module *module)
{
std::map<RTLIL::SigBit, dff_map_bit_info_t> bit_info;
SigMap sigmap(module);
}
}
-static RTLIL::Wire *add_new_wire(RTLIL::Module *module, RTLIL::IdString name, int width = 1)
+RTLIL::Wire *add_new_wire(RTLIL::Module *module, RTLIL::IdString name, int width = 1)
{
if (module->count_id(name))
log_error("Attempting to create wire %s, but a wire of this name exists already! Hint: Try another value for -sep.\n", log_id(name));
}
} ExposePass;
+PRIVATE_NAMESPACE_END
#include <string.h>
#include <algorithm>
-namespace {
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
bool inv_mode;
int verbose_level, reduce_counter, reduce_stop_at;
}
};
-} /* namespace */
-
struct FreducePass : public Pass {
FreducePass() : Pass("freduce", "perform functional reduction") { }
virtual void help()
}
} FreducePass;
+PRIVATE_NAMESPACE_END
#include "kernel/rtlil.h"
#include "kernel/log.h"
-static void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL::Design *design)
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL::Design *design)
{
bool flag_ignore_gold_x = false;
bool flag_make_outputs = false;
}
} MiterPass;
+PRIVATE_NAMESPACE_END
#include <errno.h>
#include <string.h>
-namespace {
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
struct SatHelper
{
}
};
-} /* namespace */
-
-static void print_proof_failed()
+void print_proof_failed()
{
log("\n");
log(" ______ ___ ___ _ _ _ _ \n");
log("\n");
}
-static void print_timeout()
+void print_timeout()
{
log("\n");
log(" _____ _ _ _____ ____ _ _____\n");
log("\n");
}
-static void print_qed()
+void print_qed()
{
log("\n");
log(" /$$$$$$ /$$$$$$$$ /$$$$$$$ \n");
}
} SatPass;
+PRIVATE_NAMESPACE_END
#include "kernel/sigtools.h"
#include "kernel/macc.h"
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
struct AlumaccWorker
{
RTLIL::Module *module;
}
} AlumaccPass;
+PRIVATE_NAMESPACE_END
#include <string.h>
#include <errno.h>
-using namespace PASS_DFFLIBMAP;
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
struct cell_mapping {
std::string cell_name;
}
} DfflibmapPass;
+PRIVATE_NAMESPACE_END
#include <stdio.h>
#include <string.h>
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
using RTLIL::id2cstr;
-namespace
+class SubCircuitSolver : public SubCircuit::Solver
{
- class SubCircuitSolver : public SubCircuit::Solver
- {
- public:
- bool ignore_parameters;
- std::set<std::pair<RTLIL::IdString, RTLIL::IdString>> ignored_parameters;
- std::set<RTLIL::IdString> cell_attr, wire_attr;
+public:
+ bool ignore_parameters;
+ std::set<std::pair<RTLIL::IdString, RTLIL::IdString>> ignored_parameters;
+ std::set<RTLIL::IdString> cell_attr, wire_attr;
- SubCircuitSolver() : ignore_parameters(false)
- {
- }
+ SubCircuitSolver() : ignore_parameters(false)
+ {
+ }
- bool compareAttributes(const std::set<RTLIL::IdString> &attr, const std::map<RTLIL::IdString, RTLIL::Const> &needleAttr, const std::map<RTLIL::IdString, RTLIL::Const> &haystackAttr)
- {
- for (auto &it : attr) {
- size_t nc = needleAttr.count(it), hc = haystackAttr.count(it);
- if (nc != hc || (nc > 0 && needleAttr.at(it) != haystackAttr.at(it)))
- return false;
- }
- return true;
+ bool compareAttributes(const std::set<RTLIL::IdString> &attr, const std::map<RTLIL::IdString, RTLIL::Const> &needleAttr, const std::map<RTLIL::IdString, RTLIL::Const> &haystackAttr)
+ {
+ for (auto &it : attr) {
+ size_t nc = needleAttr.count(it), hc = haystackAttr.count(it);
+ if (nc != hc || (nc > 0 && needleAttr.at(it) != haystackAttr.at(it)))
+ return false;
}
+ return true;
+ }
- RTLIL::Const unified_param(RTLIL::IdString cell_type, RTLIL::IdString param, RTLIL::Const value)
- {
- if (cell_type.substr(0, 1) != "$" || cell_type.substr(0, 2) == "$_")
- return value;
-
- #define param_bool(_n) if (param == _n) return value.as_bool();
- param_bool("\\ARST_POLARITY");
- param_bool("\\A_SIGNED");
- param_bool("\\B_SIGNED");
- param_bool("\\CLK_ENABLE");
- param_bool("\\CLK_POLARITY");
- param_bool("\\CLR_POLARITY");
- param_bool("\\EN_POLARITY");
- param_bool("\\SET_POLARITY");
- param_bool("\\TRANSPARENT");
- #undef param_bool
-
- #define param_int(_n) if (param == _n) return value.as_int();
- param_int("\\ABITS")
- param_int("\\A_WIDTH")
- param_int("\\B_WIDTH")
- param_int("\\CTRL_IN_WIDTH")
- param_int("\\CTRL_OUT_WIDTH")
- param_int("\\OFFSET")
- param_int("\\PRIORITY")
- param_int("\\RD_PORTS")
- param_int("\\SIZE")
- param_int("\\STATE_BITS")
- param_int("\\STATE_NUM")
- param_int("\\STATE_NUM_LOG2")
- param_int("\\STATE_RST")
- param_int("\\S_WIDTH")
- param_int("\\TRANS_NUM")
- param_int("\\WIDTH")
- param_int("\\WR_PORTS")
- param_int("\\Y_WIDTH")
- #undef param_int
-
+ RTLIL::Const unified_param(RTLIL::IdString cell_type, RTLIL::IdString param, RTLIL::Const value)
+ {
+ if (cell_type.substr(0, 1) != "$" || cell_type.substr(0, 2) == "$_")
return value;
- }
- virtual bool userCompareNodes(const std::string &, const std::string &, void *needleUserData,
- const std::string &, const std::string &, void *haystackUserData, const std::map<std::string, std::string> &portMapping)
- {
- RTLIL::Cell *needleCell = (RTLIL::Cell*) needleUserData;
- RTLIL::Cell *haystackCell = (RTLIL::Cell*) haystackUserData;
+ #define param_bool(_n) if (param == _n) return value.as_bool();
+ param_bool("\\ARST_POLARITY");
+ param_bool("\\A_SIGNED");
+ param_bool("\\B_SIGNED");
+ param_bool("\\CLK_ENABLE");
+ param_bool("\\CLK_POLARITY");
+ param_bool("\\CLR_POLARITY");
+ param_bool("\\EN_POLARITY");
+ param_bool("\\SET_POLARITY");
+ param_bool("\\TRANSPARENT");
+ #undef param_bool
+
+ #define param_int(_n) if (param == _n) return value.as_int();
+ param_int("\\ABITS")
+ param_int("\\A_WIDTH")
+ param_int("\\B_WIDTH")
+ param_int("\\CTRL_IN_WIDTH")
+ param_int("\\CTRL_OUT_WIDTH")
+ param_int("\\OFFSET")
+ param_int("\\PRIORITY")
+ param_int("\\RD_PORTS")
+ param_int("\\SIZE")
+ param_int("\\STATE_BITS")
+ param_int("\\STATE_NUM")
+ param_int("\\STATE_NUM_LOG2")
+ param_int("\\STATE_RST")
+ param_int("\\S_WIDTH")
+ param_int("\\TRANS_NUM")
+ param_int("\\WIDTH")
+ param_int("\\WR_PORTS")
+ param_int("\\Y_WIDTH")
+ #undef param_int
+
+ return value;
+ }
- if (!needleCell || !haystackCell) {
- log_assert(!needleCell && !haystackCell);
- return true;
- }
+ virtual bool userCompareNodes(const std::string &, const std::string &, void *needleUserData,
+ const std::string &, const std::string &, void *haystackUserData, const std::map<std::string, std::string> &portMapping)
+ {
+ RTLIL::Cell *needleCell = (RTLIL::Cell*) needleUserData;
+ RTLIL::Cell *haystackCell = (RTLIL::Cell*) haystackUserData;
- if (!ignore_parameters) {
- std::map<RTLIL::IdString, RTLIL::Const> needle_param, haystack_param;
- for (auto &it : needleCell->parameters)
- if (!ignored_parameters.count(std::pair<RTLIL::IdString, RTLIL::IdString>(needleCell->type, it.first)))
- needle_param[it.first] = unified_param(needleCell->type, it.first, it.second);
- for (auto &it : haystackCell->parameters)
- if (!ignored_parameters.count(std::pair<RTLIL::IdString, RTLIL::IdString>(haystackCell->type, it.first)))
- haystack_param[it.first] = unified_param(haystackCell->type, it.first, it.second);
- if (needle_param != haystack_param)
- return false;
- }
+ if (!needleCell || !haystackCell) {
+ log_assert(!needleCell && !haystackCell);
+ return true;
+ }
- if (cell_attr.size() > 0 && !compareAttributes(cell_attr, needleCell->attributes, haystackCell->attributes))
+ if (!ignore_parameters) {
+ std::map<RTLIL::IdString, RTLIL::Const> needle_param, haystack_param;
+ for (auto &it : needleCell->parameters)
+ if (!ignored_parameters.count(std::pair<RTLIL::IdString, RTLIL::IdString>(needleCell->type, it.first)))
+ needle_param[it.first] = unified_param(needleCell->type, it.first, it.second);
+ for (auto &it : haystackCell->parameters)
+ if (!ignored_parameters.count(std::pair<RTLIL::IdString, RTLIL::IdString>(haystackCell->type, it.first)))
+ haystack_param[it.first] = unified_param(haystackCell->type, it.first, it.second);
+ if (needle_param != haystack_param)
return false;
+ }
- if (wire_attr.size() > 0)
- {
- RTLIL::Wire *lastNeedleWire = NULL;
- RTLIL::Wire *lastHaystackWire = NULL;
- std::map<RTLIL::IdString, RTLIL::Const> emptyAttr;
+ if (cell_attr.size() > 0 && !compareAttributes(cell_attr, needleCell->attributes, haystackCell->attributes))
+ return false;
- for (auto &conn : needleCell->connections())
- {
- RTLIL::SigSpec needleSig = conn.second;
- RTLIL::SigSpec haystackSig = haystackCell->getPort(portMapping.at(conn.first.str()));
-
- for (int i = 0; i < std::min(needleSig.size(), haystackSig.size()); i++) {
- RTLIL::Wire *needleWire = needleSig[i].wire, *haystackWire = haystackSig[i].wire;
- if (needleWire != lastNeedleWire || haystackWire != lastHaystackWire)
- if (!compareAttributes(wire_attr, needleWire ? needleWire->attributes : emptyAttr, haystackWire ? haystackWire->attributes : emptyAttr))
- return false;
- lastNeedleWire = needleWire, lastHaystackWire = haystackWire;
- }
+ if (wire_attr.size() > 0)
+ {
+ RTLIL::Wire *lastNeedleWire = NULL;
+ RTLIL::Wire *lastHaystackWire = NULL;
+ std::map<RTLIL::IdString, RTLIL::Const> emptyAttr;
+
+ for (auto &conn : needleCell->connections())
+ {
+ RTLIL::SigSpec needleSig = conn.second;
+ RTLIL::SigSpec haystackSig = haystackCell->getPort(portMapping.at(conn.first.str()));
+
+ for (int i = 0; i < std::min(needleSig.size(), haystackSig.size()); i++) {
+ RTLIL::Wire *needleWire = needleSig[i].wire, *haystackWire = haystackSig[i].wire;
+ if (needleWire != lastNeedleWire || haystackWire != lastHaystackWire)
+ if (!compareAttributes(wire_attr, needleWire ? needleWire->attributes : emptyAttr, haystackWire ? haystackWire->attributes : emptyAttr))
+ return false;
+ lastNeedleWire = needleWire, lastHaystackWire = haystackWire;
}
}
-
- return true;
}
- };
- struct bit_ref_t {
- std::string cell, port;
- int bit;
- };
+ return true;
+ }
+};
- bool module2graph(SubCircuit::Graph &graph, RTLIL::Module *mod, bool constports, RTLIL::Design *sel = NULL,
- int max_fanout = -1, std::set<std::pair<RTLIL::IdString, RTLIL::IdString>> *split = NULL)
- {
- SigMap sigmap(mod);
- std::map<RTLIL::SigBit, bit_ref_t> sig_bit_ref;
+struct bit_ref_t {
+ std::string cell, port;
+ int bit;
+};
- if (sel && !sel->selected(mod)) {
- log(" Skipping module %s as it is not selected.\n", id2cstr(mod->name));
- return false;
- }
+bool module2graph(SubCircuit::Graph &graph, RTLIL::Module *mod, bool constports, RTLIL::Design *sel = NULL,
+ int max_fanout = -1, std::set<std::pair<RTLIL::IdString, RTLIL::IdString>> *split = NULL)
+{
+ SigMap sigmap(mod);
+ std::map<RTLIL::SigBit, bit_ref_t> sig_bit_ref;
- if (mod->processes.size() > 0) {
- log(" Skipping module %s as it contains unprocessed processes.\n", id2cstr(mod->name));
- return false;
- }
+ if (sel && !sel->selected(mod)) {
+ log(" Skipping module %s as it is not selected.\n", id2cstr(mod->name));
+ return false;
+ }
- if (constports) {
- graph.createNode("$const$0", "$const$0", NULL, true);
- graph.createNode("$const$1", "$const$1", NULL, true);
- graph.createNode("$const$x", "$const$x", NULL, true);
- graph.createNode("$const$z", "$const$z", NULL, true);
- graph.createPort("$const$0", "\\Y", 1);
- graph.createPort("$const$1", "\\Y", 1);
- graph.createPort("$const$x", "\\Y", 1);
- graph.createPort("$const$z", "\\Y", 1);
- graph.markExtern("$const$0", "\\Y", 0);
- graph.markExtern("$const$1", "\\Y", 0);
- graph.markExtern("$const$x", "\\Y", 0);
- graph.markExtern("$const$z", "\\Y", 0);
- }
+ if (mod->processes.size() > 0) {
+ log(" Skipping module %s as it contains unprocessed processes.\n", id2cstr(mod->name));
+ return false;
+ }
- std::map<std::pair<RTLIL::Wire*, int>, int> sig_use_count;
- if (max_fanout > 0)
- for (auto &cell_it : mod->cells_)
- {
- RTLIL::Cell *cell = cell_it.second;
- if (!sel || sel->selected(mod, cell))
- for (auto &conn : cell->connections()) {
- RTLIL::SigSpec conn_sig = conn.second;
- sigmap.apply(conn_sig);
- for (auto &bit : conn_sig)
- if (bit.wire != NULL)
- sig_use_count[std::pair<RTLIL::Wire*, int>(bit.wire, bit.offset)]++;
- }
- }
+ if (constports) {
+ graph.createNode("$const$0", "$const$0", NULL, true);
+ graph.createNode("$const$1", "$const$1", NULL, true);
+ graph.createNode("$const$x", "$const$x", NULL, true);
+ graph.createNode("$const$z", "$const$z", NULL, true);
+ graph.createPort("$const$0", "\\Y", 1);
+ graph.createPort("$const$1", "\\Y", 1);
+ graph.createPort("$const$x", "\\Y", 1);
+ graph.createPort("$const$z", "\\Y", 1);
+ graph.markExtern("$const$0", "\\Y", 0);
+ graph.markExtern("$const$1", "\\Y", 0);
+ graph.markExtern("$const$x", "\\Y", 0);
+ graph.markExtern("$const$z", "\\Y", 0);
+ }
- // create graph nodes from cells
+ std::map<std::pair<RTLIL::Wire*, int>, int> sig_use_count;
+ if (max_fanout > 0)
for (auto &cell_it : mod->cells_)
{
RTLIL::Cell *cell = cell_it.second;
- if (sel && !sel->selected(mod, cell))
- continue;
+ if (!sel || sel->selected(mod, cell))
+ for (auto &conn : cell->connections()) {
+ RTLIL::SigSpec conn_sig = conn.second;
+ sigmap.apply(conn_sig);
+ for (auto &bit : conn_sig)
+ if (bit.wire != NULL)
+ sig_use_count[std::pair<RTLIL::Wire*, int>(bit.wire, bit.offset)]++;
+ }
+ }
- std::string type = cell->type.str();
- if (sel == NULL && type.substr(0, 2) == "\\$")
- type = type.substr(1);
- graph.createNode(cell->name.str(), type, (void*)cell);
+ // create graph nodes from cells
+ for (auto &cell_it : mod->cells_)
+ {
+ RTLIL::Cell *cell = cell_it.second;
+ if (sel && !sel->selected(mod, cell))
+ continue;
- for (auto &conn : cell->connections())
- {
- graph.createPort(cell->name.str(), conn.first.str(), conn.second.size());
+ std::string type = cell->type.str();
+ if (sel == NULL && type.substr(0, 2) == "\\$")
+ type = type.substr(1);
+ graph.createNode(cell->name.str(), type, (void*)cell);
- if (split && split->count(std::pair<RTLIL::IdString, RTLIL::IdString>(cell->type, conn.first)) > 0)
- continue;
+ for (auto &conn : cell->connections())
+ {
+ graph.createPort(cell->name.str(), conn.first.str(), conn.second.size());
- RTLIL::SigSpec conn_sig = conn.second;
- sigmap.apply(conn_sig);
+ if (split && split->count(std::pair<RTLIL::IdString, RTLIL::IdString>(cell->type, conn.first)) > 0)
+ continue;
- for (int i = 0; i < conn_sig.size(); i++)
- {
- auto &bit = conn_sig[i];
-
- if (bit.wire == NULL) {
- if (constports) {
- std::string node = "$const$x";
- if (bit == RTLIL::State::S0) node = "$const$0";
- if (bit == RTLIL::State::S1) node = "$const$1";
- if (bit == RTLIL::State::Sz) node = "$const$z";
- graph.createConnection(cell->name.str(), conn.first.str(), i, node, "\\Y", 0);
- } else
- graph.createConstant(cell->name.str(), conn.first.str(), i, int(bit.data));
- continue;
- }
+ RTLIL::SigSpec conn_sig = conn.second;
+ sigmap.apply(conn_sig);
- if (max_fanout > 0 && sig_use_count[std::pair<RTLIL::Wire*, int>(bit.wire, bit.offset)] > max_fanout)
- continue;
+ for (int i = 0; i < conn_sig.size(); i++)
+ {
+ auto &bit = conn_sig[i];
+
+ if (bit.wire == NULL) {
+ if (constports) {
+ std::string node = "$const$x";
+ if (bit == RTLIL::State::S0) node = "$const$0";
+ if (bit == RTLIL::State::S1) node = "$const$1";
+ if (bit == RTLIL::State::Sz) node = "$const$z";
+ graph.createConnection(cell->name.str(), conn.first.str(), i, node, "\\Y", 0);
+ } else
+ graph.createConstant(cell->name.str(), conn.first.str(), i, int(bit.data));
+ continue;
+ }
- if (sel && !sel->selected(mod, bit.wire))
- continue;
+ if (max_fanout > 0 && sig_use_count[std::pair<RTLIL::Wire*, int>(bit.wire, bit.offset)] > max_fanout)
+ continue;
- if (sig_bit_ref.count(bit) == 0) {
- bit_ref_t &bit_ref = sig_bit_ref[bit];
- bit_ref.cell = cell->name.str();
- bit_ref.port = conn.first.str();
- bit_ref.bit = i;
- }
+ if (sel && !sel->selected(mod, bit.wire))
+ continue;
+ if (sig_bit_ref.count(bit) == 0) {
bit_ref_t &bit_ref = sig_bit_ref[bit];
- graph.createConnection(bit_ref.cell, bit_ref.port, bit_ref.bit, cell->name.str(), conn.first.str(), i);
+ bit_ref.cell = cell->name.str();
+ bit_ref.port = conn.first.str();
+ bit_ref.bit = i;
}
- }
- }
-
- // mark external signals (used in non-selected cells)
- for (auto &cell_it : mod->cells_)
- {
- RTLIL::Cell *cell = cell_it.second;
- if (sel && !sel->selected(mod, cell))
- for (auto &conn : cell->connections())
- {
- RTLIL::SigSpec conn_sig = conn.second;
- sigmap.apply(conn_sig);
- for (auto &bit : conn_sig)
- if (sig_bit_ref.count(bit) != 0) {
- bit_ref_t &bit_ref = sig_bit_ref[bit];
- graph.markExtern(bit_ref.cell, bit_ref.port, bit_ref.bit);
- }
- }
+ bit_ref_t &bit_ref = sig_bit_ref[bit];
+ graph.createConnection(bit_ref.cell, bit_ref.port, bit_ref.bit, cell->name.str(), conn.first.str(), i);
+ }
}
+ }
- // mark external signals (used in module ports)
- for (auto &wire_it : mod->wires_)
- {
- RTLIL::Wire *wire = wire_it.second;
- if (wire->port_id > 0)
+ // mark external signals (used in non-selected cells)
+ for (auto &cell_it : mod->cells_)
+ {
+ RTLIL::Cell *cell = cell_it.second;
+ if (sel && !sel->selected(mod, cell))
+ for (auto &conn : cell->connections())
{
- RTLIL::SigSpec conn_sig(wire);
+ RTLIL::SigSpec conn_sig = conn.second;
sigmap.apply(conn_sig);
for (auto &bit : conn_sig)
graph.markExtern(bit_ref.cell, bit_ref.port, bit_ref.bit);
}
}
- }
-
- // graph.print();
- return true;
}
- RTLIL::Cell *replace(RTLIL::Module *needle, RTLIL::Module *haystack, SubCircuit::Solver::Result &match)
+ // mark external signals (used in module ports)
+ for (auto &wire_it : mod->wires_)
{
- SigMap sigmap(needle);
- SigSet<std::pair<RTLIL::IdString, int>> sig2port;
-
- // create new cell
- RTLIL::Cell *cell = haystack->addCell(stringf("$extract$%s$%d", needle->name.c_str(), autoidx++), needle->name);
-
- // create cell ports
- for (auto &it : needle->wires_) {
- RTLIL::Wire *wire = it.second;
- if (wire->port_id > 0) {
- for (int i = 0; i < wire->width; i++)
- sig2port.insert(sigmap(RTLIL::SigSpec(wire, i)), std::pair<RTLIL::IdString, int>(wire->name, i));
- cell->setPort(wire->name, RTLIL::SigSpec(RTLIL::State::Sz, wire->width));
- }
+ RTLIL::Wire *wire = wire_it.second;
+ if (wire->port_id > 0)
+ {
+ RTLIL::SigSpec conn_sig(wire);
+ sigmap.apply(conn_sig);
+
+ for (auto &bit : conn_sig)
+ if (sig_bit_ref.count(bit) != 0) {
+ bit_ref_t &bit_ref = sig_bit_ref[bit];
+ graph.markExtern(bit_ref.cell, bit_ref.port, bit_ref.bit);
+ }
}
+ }
- // delete replaced cells and connect new ports
- for (auto &it : match.mappings)
- {
- auto &mapping = it.second;
- RTLIL::Cell *needle_cell = (RTLIL::Cell*)mapping.needleUserData;
- RTLIL::Cell *haystack_cell = (RTLIL::Cell*)mapping.haystackUserData;
+ // graph.print();
+ return true;
+}
- if (needle_cell == NULL)
- continue;
+RTLIL::Cell *replace(RTLIL::Module *needle, RTLIL::Module *haystack, SubCircuit::Solver::Result &match)
+{
+ SigMap sigmap(needle);
+ SigSet<std::pair<RTLIL::IdString, int>> sig2port;
+
+ // create new cell
+ RTLIL::Cell *cell = haystack->addCell(stringf("$extract$%s$%d", needle->name.c_str(), autoidx++), needle->name);
+
+ // create cell ports
+ for (auto &it : needle->wires_) {
+ RTLIL::Wire *wire = it.second;
+ if (wire->port_id > 0) {
+ for (int i = 0; i < wire->width; i++)
+ sig2port.insert(sigmap(RTLIL::SigSpec(wire, i)), std::pair<RTLIL::IdString, int>(wire->name, i));
+ cell->setPort(wire->name, RTLIL::SigSpec(RTLIL::State::Sz, wire->width));
+ }
+ }
- for (auto &conn : needle_cell->connections()) {
- RTLIL::SigSpec sig = sigmap(conn.second);
- if (mapping.portMapping.count(conn.first.str()) > 0 && sig2port.has(sigmap(sig))) {
- for (int i = 0; i < sig.size(); i++)
- for (auto &port : sig2port.find(sig[i])) {
- RTLIL::SigSpec bitsig = haystack_cell->getPort(mapping.portMapping[conn.first.str()]).extract(i, 1);
- RTLIL::SigSpec new_sig = cell->getPort(port.first);
- new_sig.replace(port.second, bitsig);
- cell->setPort(port.first, new_sig);
- }
+ // delete replaced cells and connect new ports
+ for (auto &it : match.mappings)
+ {
+ auto &mapping = it.second;
+ RTLIL::Cell *needle_cell = (RTLIL::Cell*)mapping.needleUserData;
+ RTLIL::Cell *haystack_cell = (RTLIL::Cell*)mapping.haystackUserData;
+
+ if (needle_cell == NULL)
+ continue;
+
+ for (auto &conn : needle_cell->connections()) {
+ RTLIL::SigSpec sig = sigmap(conn.second);
+ if (mapping.portMapping.count(conn.first.str()) > 0 && sig2port.has(sigmap(sig))) {
+ for (int i = 0; i < sig.size(); i++)
+ for (auto &port : sig2port.find(sig[i])) {
+ RTLIL::SigSpec bitsig = haystack_cell->getPort(mapping.portMapping[conn.first.str()]).extract(i, 1);
+ RTLIL::SigSpec new_sig = cell->getPort(port.first);
+ new_sig.replace(port.second, bitsig);
+ cell->setPort(port.first, new_sig);
}
}
-
- haystack->remove(haystack_cell);
}
- return cell;
+ haystack->remove(haystack_cell);
}
- bool compareSortNeedleList(RTLIL::Module *left, RTLIL::Module *right)
- {
- int left_idx = 0, right_idx = 0;
- if (left->attributes.count("\\extract_order") > 0)
- left_idx = left->attributes.at("\\extract_order").as_int();
- if (right->attributes.count("\\extract_order") > 0)
- right_idx = right->attributes.at("\\extract_order").as_int();
- if (left_idx != right_idx)
- return left_idx < right_idx;
- return left->name < right->name;
- }
+ return cell;
+}
+
+bool compareSortNeedleList(RTLIL::Module *left, RTLIL::Module *right)
+{
+ int left_idx = 0, right_idx = 0;
+ if (left->attributes.count("\\extract_order") > 0)
+ left_idx = left->attributes.at("\\extract_order").as_int();
+ if (right->attributes.count("\\extract_order") > 0)
+ right_idx = right->attributes.at("\\extract_order").as_int();
+ if (left_idx != right_idx)
+ return left_idx < right_idx;
+ return left->name < right->name;
}
struct ExtractPass : public Pass {
}
} ExtractPass;
+PRIVATE_NAMESPACE_END
#include "kernel/rtlil.h"
#include "kernel/log.h"
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
static std::string hicell_celltype, hicell_portname;
static std::string locell_celltype, locell_portname;
static bool singleton_mode;
}
} HilomapPass;
+PRIVATE_NAMESPACE_END
#include "kernel/rtlil.h"
#include "kernel/log.h"
-static void split_portname_pair(std::string &port1, std::string &port2)
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+void split_portname_pair(std::string &port1, std::string &port2)
{
size_t pos = port1.find_first_of(':');
if (pos != std::string::npos) {
}
} IopadmapPass;
+PRIVATE_NAMESPACE_END
#include "kernel/log.h"
#endif
-using namespace PASS_DFFLIBMAP;
+using namespace Yosys;
std::set<std::string> LibertyAst::blacklist;
std::set<std::string> LibertyAst::whitelist;
#include <vector>
#include <set>
-namespace PASS_DFFLIBMAP
+namespace Yosys
{
struct LibertyAst
{
#include "kernel/yosys.h"
#include "kernel/macc.h"
-extern void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap = false);
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
struct MaccmapWorker
{
}
};
+PRIVATE_NAMESPACE_END
+YOSYS_NAMESPACE_BEGIN
+
+extern void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap = false);
+
void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap)
{
int width = SIZE(cell->getPort("\\Y"));
}
}
+YOSYS_NAMESPACE_END
+PRIVATE_NAMESPACE_BEGIN
+
struct MaccmapPass : public Pass {
MaccmapPass() : Pass("maccmap", "mapping macc cells") { }
virtual void help()
}
} MaccmapPass;
+PRIVATE_NAMESPACE_END
#include <stdio.h>
#include <string.h>
-extern void simplemap_get_mappers(std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers);
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
static void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell)
{
}
}
+PRIVATE_NAMESPACE_END
+YOSYS_NAMESPACE_BEGIN
+
+extern void simplemap_get_mappers(std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers);
+
void simplemap_get_mappers(std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers)
{
mappers["$not"] = simplemap_not;
mappers["$dlatch"] = simplemap_dlatch;
}
+YOSYS_NAMESPACE_END
+PRIVATE_NAMESPACE_BEGIN
+
struct SimplemapPass : public Pass {
SimplemapPass() : Pass("simplemap", "mapping simple coarse-grain cells") { }
virtual void help()
}
} SimplemapPass;
+PRIVATE_NAMESPACE_END
#include "passes/techmap/techmap.inc"
+YOSYS_NAMESPACE_BEGIN
+
// see simplemap.cc
extern void simplemap_get_mappers(std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers);
// see maccmap.cc
extern void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap = false);
-static void apply_prefix(std::string prefix, std::string &id)
+YOSYS_NAMESPACE_END
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+void apply_prefix(std::string prefix, std::string &id)
{
if (id[0] == '\\')
id = prefix + "." + id.substr(1);
id = "$techmap" + prefix + "." + id;
}
-static void apply_prefix(std::string prefix, RTLIL::SigSpec &sig, RTLIL::Module *module)
+void apply_prefix(std::string prefix, RTLIL::SigSpec &sig, RTLIL::Module *module)
{
std::vector<RTLIL::SigChunk> chunks = sig;
for (auto &chunk : chunks)
}
} FlattenPass;
+PRIVATE_NAMESPACE_END
#include "kernel/yosys.h"
#include "kernel/satgen.h"
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
static uint32_t xorshift32_state = 123456789;
static uint32_t xorshift32(uint32_t limit) {
}
} TestAbcloopPass;
+PRIVATE_NAMESPACE_END
#include <stdio.h>
#include <time.h>
+USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
static std::string id(std::string internal_id)
#include "kernel/macc.h"
#include <algorithm>
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
static uint32_t xorshift32_state = 123456789;
static uint32_t xorshift32(uint32_t limit) {
}
} TestCellPass;
+PRIVATE_NAMESPACE_END
#include "kernel/rtlil.h"
#include "kernel/log.h"
-static bool check_label(bool &active, std::string run_from, std::string run_to, std::string label)
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+bool check_label(bool &active, std::string run_from, std::string run_to, std::string label)
{
if (!run_from.empty() && run_from == run_to) {
active = (label == run_from);
}
} SynthPass;
+PRIVATE_NAMESPACE_END
#include "kernel/rtlil.h"
#include "kernel/log.h"
-static bool check_label(bool &active, std::string run_from, std::string run_to, std::string label)
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+bool check_label(bool &active, std::string run_from, std::string run_to, std::string label)
{
if (label == run_from)
active = true;
}
} SynthXilinxPass;
+PRIVATE_NAMESPACE_END
projects / yosys.git / commitdiff