Move the estimate functions out of the tables and kill the tables.
static int
gen6_pipeline_estimate_commands(const struct ilo_3d_pipeline *p,
- const struct ilo_gpe_gen6 *gen6,
const struct ilo_context *ilo)
{
static int size;
}
if (count)
- size += gen6->estimate_command_size(p->dev, cmd, count);
+ size += ilo_gpe_gen6_estimate_command_size(p->dev, cmd, count);
}
return size;
static int
gen6_pipeline_estimate_states(const struct ilo_3d_pipeline *p,
- const struct ilo_gpe_gen6 *gen6,
const struct ilo_context *ilo)
{
static int static_size;
int i;
for (i = 0; i < Elements(static_states); i++) {
- static_size += gen6->estimate_state_size(p->dev,
+ static_size += ilo_gpe_gen6_estimate_state_size(p->dev,
static_states[i].state,
static_states[i].count);
}
}
if (count) {
- size += gen6->estimate_state_size(p->dev,
+ size += ilo_gpe_gen6_estimate_state_size(p->dev,
ILO_GPE_GEN6_SURFACE_STATE, count);
}
for (shader_type = 0; shader_type < PIPE_SHADER_TYPES; shader_type++) {
count = ilo->sampler[shader_type].count;
if (count) {
- size += gen6->estimate_state_size(p->dev,
+ size += ilo_gpe_gen6_estimate_state_size(p->dev,
ILO_GPE_GEN6_SAMPLER_BORDER_COLOR_STATE, count);
- size += gen6->estimate_state_size(p->dev,
+ size += ilo_gpe_gen6_estimate_state_size(p->dev,
ILO_GPE_GEN6_SAMPLER_STATE, count);
}
}
const int pcb_size =
ilo_shader_get_kernel_param(ilo->vs, ILO_KERNEL_VS_PCB_UCP_SIZE);
- size += gen6->estimate_state_size(p->dev,
+ size += ilo_gpe_gen6_estimate_state_size(p->dev,
ILO_GPE_GEN6_PUSH_CONSTANT_BUFFER, pcb_size);
}
enum ilo_3d_pipeline_action action,
const void *arg)
{
- const struct ilo_gpe_gen6 *gen6 = ilo_gpe_gen6_get();
int size;
switch (action) {
{
const struct ilo_context *ilo = arg;
- size = gen6_pipeline_estimate_commands(p, gen6, ilo) +
- gen6_pipeline_estimate_states(p, gen6, ilo);
+ size = gen6_pipeline_estimate_commands(p, ilo) +
+ gen6_pipeline_estimate_states(p, ilo);
}
break;
case ILO_3D_PIPELINE_FLUSH:
- size = gen6->estimate_command_size(p->dev,
+ size = ilo_gpe_gen6_estimate_command_size(p->dev,
ILO_GPE_GEN6_PIPE_CONTROL, 1) * 3;
break;
case ILO_3D_PIPELINE_WRITE_TIMESTAMP:
- size = gen6->estimate_command_size(p->dev,
+ size = ilo_gpe_gen6_estimate_command_size(p->dev,
ILO_GPE_GEN6_PIPE_CONTROL, 1) * 2;
break;
case ILO_3D_PIPELINE_WRITE_DEPTH_COUNT:
- size = gen6->estimate_command_size(p->dev,
+ size = ilo_gpe_gen6_estimate_command_size(p->dev,
ILO_GPE_GEN6_PIPE_CONTROL, 1) * 3;
break;
default:
static int
gen7_pipeline_estimate_commands(const struct ilo_3d_pipeline *p,
- const struct ilo_gpe_gen7 *gen7,
const struct ilo_context *ilo)
{
static int size;
}
if (count) {
- size += gen7->estimate_command_size(p->dev,
+ size += ilo_gpe_gen7_estimate_command_size(p->dev,
cmd, count);
}
}
static int
gen7_pipeline_estimate_states(const struct ilo_3d_pipeline *p,
- const struct ilo_gpe_gen7 *gen7,
const struct ilo_context *ilo)
{
static int static_size;
int i;
for (i = 0; i < Elements(static_states); i++) {
- static_size += gen7->estimate_state_size(p->dev,
+ static_size += ilo_gpe_gen7_estimate_state_size(p->dev,
static_states[i].state,
static_states[i].count);
}
}
if (count) {
- size += gen7->estimate_state_size(p->dev,
+ size += ilo_gpe_gen7_estimate_state_size(p->dev,
ILO_GPE_GEN7_SURFACE_STATE, count);
}
for (shader_type = 0; shader_type < PIPE_SHADER_TYPES; shader_type++) {
count = ilo->sampler[shader_type].count;
if (count) {
- size += gen7->estimate_state_size(p->dev,
+ size += ilo_gpe_gen7_estimate_state_size(p->dev,
ILO_GPE_GEN7_SAMPLER_BORDER_COLOR_STATE, count);
- size += gen7->estimate_state_size(p->dev,
+ size += ilo_gpe_gen7_estimate_state_size(p->dev,
ILO_GPE_GEN7_SAMPLER_STATE, count);
}
}
const int pcb_size =
ilo_shader_get_kernel_param(ilo->vs, ILO_KERNEL_VS_PCB_UCP_SIZE);
- size += gen7->estimate_state_size(p->dev,
+ size += ilo_gpe_gen7_estimate_state_size(p->dev,
ILO_GPE_GEN7_PUSH_CONSTANT_BUFFER, pcb_size);
}
enum ilo_3d_pipeline_action action,
const void *arg)
{
- const struct ilo_gpe_gen7 *gen7 = ilo_gpe_gen7_get();
int size;
switch (action) {
{
const struct ilo_context *ilo = arg;
- size = gen7_pipeline_estimate_commands(p, gen7, ilo) +
- gen7_pipeline_estimate_states(p, gen7, ilo);
+ size = gen7_pipeline_estimate_commands(p, ilo) +
+ gen7_pipeline_estimate_states(p, ilo);
}
break;
case ILO_3D_PIPELINE_FLUSH:
case ILO_3D_PIPELINE_WRITE_TIMESTAMP:
case ILO_3D_PIPELINE_WRITE_DEPTH_COUNT:
- size = gen7->estimate_command_size(p->dev,
+ size = ilo_gpe_gen7_estimate_command_size(p->dev,
ILO_GPE_GEN7_PIPE_CONTROL, 1);
break;
default:
}
}
-static int
-gen6_estimate_command_size(const struct ilo_dev_info *dev,
- enum ilo_gpe_gen6_command cmd,
- int arg)
+int
+ilo_gpe_gen6_estimate_command_size(const struct ilo_dev_info *dev,
+ enum ilo_gpe_gen6_command cmd,
+ int arg)
{
static const struct {
int header;
return (likely(count)) ? header + body * count : 0;
}
-static int
-gen6_estimate_state_size(const struct ilo_dev_info *dev,
- enum ilo_gpe_gen6_state state,
- int arg)
+int
+ilo_gpe_gen6_estimate_state_size(const struct ilo_dev_info *dev,
+ enum ilo_gpe_gen6_state state,
+ int arg)
{
static const struct {
int alignment;
return estimate;
}
-
-static const struct ilo_gpe_gen6 gen6_gpe = {
- .estimate_command_size = gen6_estimate_command_size,
- .estimate_state_size = gen6_estimate_state_size,
-};
-
-const struct ilo_gpe_gen6 *
-ilo_gpe_gen6_get(void)
-{
- return &gen6_gpe;
-}
ILO_GPE_GEN6_STATE_COUNT,
};
-/**
- * GEN6 graphics processing engine
- *
- * This is a low-level interface. It does not handle the interdependencies
- * between states.
- */
-struct ilo_gpe_gen6 {
- int (*estimate_command_size)(const struct ilo_dev_info *dev,
- enum ilo_gpe_gen6_command cmd,
- int arg);
-
- int (*estimate_state_size)(const struct ilo_dev_info *dev,
- enum ilo_gpe_gen6_state state,
- int arg);
-};
-
-const struct ilo_gpe_gen6 *
-ilo_gpe_gen6_get(void);
-
-/* Below are helpers for other GENs */
+int
+ilo_gpe_gen6_estimate_command_size(const struct ilo_dev_info *dev,
+ enum ilo_gpe_gen6_command cmd,
+ int arg);
+
+int
+ilo_gpe_gen6_estimate_state_size(const struct ilo_dev_info *dev,
+ enum ilo_gpe_gen6_state state,
+ int arg);
/**
* Translate winsys tiling to hardware tiling.
surf->bo = tex->bo;
}
-static int
-gen7_estimate_command_size(const struct ilo_dev_info *dev,
- enum ilo_gpe_gen7_command cmd,
- int arg)
+int
+ilo_gpe_gen7_estimate_command_size(const struct ilo_dev_info *dev,
+ enum ilo_gpe_gen7_command cmd,
+ int arg)
{
static const struct {
int header;
return (likely(count)) ? header + body * count : 0;
}
-static int
-gen7_estimate_state_size(const struct ilo_dev_info *dev,
- enum ilo_gpe_gen7_state state,
- int arg)
+int
+ilo_gpe_gen7_estimate_state_size(const struct ilo_dev_info *dev,
+ enum ilo_gpe_gen7_state state,
+ int arg)
{
static const struct {
int alignment;
return estimate;
}
-
-static void
-gen7_init(struct ilo_gpe_gen7 *gen7)
-{
- gen7->estimate_command_size = gen7_estimate_command_size;
- gen7->estimate_state_size = gen7_estimate_state_size;
-}
-
-static struct ilo_gpe_gen7 gen7_gpe;
-
-const struct ilo_gpe_gen7 *
-ilo_gpe_gen7_get(void)
-{
- if (!gen7_gpe.estimate_command_size)
- gen7_init(&gen7_gpe);
-
- return &gen7_gpe;
-}
ILO_GPE_GEN7_STATE_COUNT,
};
-/**
- * GEN7 graphics processing engine
- *
- * \see ilo_gpe_gen6
- */
-struct ilo_gpe_gen7 {
- int (*estimate_command_size)(const struct ilo_dev_info *dev,
- enum ilo_gpe_gen7_command cmd,
- int arg);
-
- int (*estimate_state_size)(const struct ilo_dev_info *dev,
- enum ilo_gpe_gen7_state state,
- int arg);
-};
-
-const struct ilo_gpe_gen7 *
-ilo_gpe_gen7_get(void);
+int
+ilo_gpe_gen7_estimate_command_size(const struct ilo_dev_info *dev,
+ enum ilo_gpe_gen7_command cmd,
+ int arg);
+
+int
+ilo_gpe_gen7_estimate_state_size(const struct ilo_dev_info *dev,
+ enum ilo_gpe_gen7_state state,
+ int arg);
static inline void
gen7_emit_GPGPU_WALKER(const struct ilo_dev_info *dev,