Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_required

diff --cc backends/aiger/xaiger.cc
Simple merge

diff --cc passes/techmap/abc9.cc
Simple merge

diff --cc passes/techmap/abc9_exe.cc
Simple merge

diff --cc passes/techmap/abc9_ops.cc
index eac1ff2b6318d0dbb279c50f4286568a83062d0a,cc22fd474ab913aa2edb8700932214fe5182088f..7f3bbc7ad56c65f598669119cdfba86d0c871323
--- 1/passes/techmap/abc9_ops.cc
--- 2/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@@ -377,54 -319,78 +378,70 @@@ void prep_holes(RTLIL::Module *module, 
                log_assert(orig_box_module);
                IdString derived_name = orig_box_module->derive(design, cell->parameters);
                RTLIL::Module* box_module = design->module(derived_name);
-               cell->type = derived_name;
-               cell->parameters.clear();
- 
-               int box_inputs = 0;
-               auto r = cell_cache.insert(std::make_pair(derived_name, nullptr));
-               Cell *holes_cell = r.first->second;
-               if (r.second && box_module->get_bool_attribute("\\whitebox")) {
-                       holes_cell = holes_module->addCell(cell->name, cell->type);
-                       holes_cell->parameters = cell->parameters;
-                       r.first->second = holes_cell;
- 
-                       if (box_module->has_processes())
-                               Pass::call_on_module(design, box_module, "proc");
-               }
++              //cell->type = derived_name;
++              //cell->parameters.clear();
  
-               auto r2 = box_ports.insert(cell->type);
-               if (r2.second) {
-                       // Make carry in the last PI, and carry out the last PO
-                       //   since ABC requires it this way
-                       IdString carry_in, carry_out;
-                       for (const auto &port_name : box_module->ports) {
-                               auto w = box_module->wire(port_name);
-                               log_assert(w);
-                               if (w->get_bool_attribute("\\abc9_carry")) {
-                                       if (w->port_input)
-                                               carry_in = port_name;
-                                       if (w->port_output)
-                                               carry_out = port_name;
+               auto r = cell_cache.insert(derived_name);
+               auto &holes_cell = r.first->second;
+               if (r.second) {
 -                      if (box_module->has_processes())
 -                              Pass::call_on_module(design, box_module, "proc");
 -
+                       auto r2 = box_ports.insert(cell->type);
+                       if (r2.second) {
+                               // Make carry in the last PI, and carry out the last PO
+                               //   since ABC requires it this way
+                               IdString carry_in, carry_out;
+                               for (const auto &port_name : box_module->ports) {
+                                       auto w = box_module->wire(port_name);
+                                       log_assert(w);
+                                       if (w->get_bool_attribute("\\abc9_carry")) {
 -                                              if (w->port_input) {
 -                                                      if (carry_in != IdString())
 -                                                              log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(box_module));
++                                              if (w->port_input)
+                                                       carry_in = port_name;
 -                                              }
 -                                              if (w->port_output) {
 -                                                      if (carry_out != IdString())
 -                                                              log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(box_module));
++                                              if (w->port_output)
+                                                       carry_out = port_name;
 -                                              }
+                                       }
+                                       else
+                                               r2.first->second.push_back(port_name);
                                }
-                               else
-                                       r2.first->second.push_back(port_name);
-                       }
  
-                       if (carry_in != IdString()) {
-                               r2.first->second.push_back(carry_in);
-                               r2.first->second.push_back(carry_out);
 -                              if (carry_in != IdString() && carry_out == IdString())
 -                                      log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(box_module));
 -                              if (carry_in == IdString() && carry_out != IdString())
 -                                      log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(box_module));
+                               if (carry_in != IdString()) {
+                                       r2.first->second.push_back(carry_in);
+                                       r2.first->second.push_back(carry_out);
+                               }
                        }
-               }
  
-               for (const auto &port_name : box_ports.at(cell->type)) {
-                       RTLIL::Wire *w = box_module->wire(port_name);
-                       log_assert(w);
-                       RTLIL::Wire *holes_wire;
-                       RTLIL::SigSpec port_sig;
-                       if (w->port_input)
-                               for (int i = 0; i < GetSize(w); i++) {
+                       if (box_module->get_bool_attribute("\\whitebox")) {
+                               holes_cell = holes_module->addCell(cell->name, derived_name);
+ 
++                              if (box_module->has_processes())
++                                      Pass::call_on_module(design, box_module, "proc");
++
+                               int box_inputs = 0;
+                               for (auto port_name : box_ports.at(cell->type)) {
+                                       RTLIL::Wire *w = box_module->wire(port_name);
+                                       log_assert(w);
+                                       log_assert(!w->port_input || !w->port_output);
+                                       auto &conn = holes_cell->connections_[port_name];
+                                       if (w->port_input) {
+                                               for (int i = 0; i < GetSize(w); i++) {
+                                                       box_inputs++;
+                                                       RTLIL::Wire *holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
+                                                       if (!holes_wire) {
+                                                               holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
+                                                               holes_wire->port_input = true;
+                                                               holes_wire->port_id = port_id++;
+                                                               holes_module->ports.push_back(holes_wire->name);
+                                                       }
+                                                       conn.append(holes_wire);
+                                               }
+                                       }
+                                       else if (w->port_output)
+                                               conn = holes_module->addWire(stringf("%s.%s", derived_name.c_str(), log_id(port_name)), GetSize(w));
+                               }
+ 
+                               // For flops only, create an extra 1-bit input that drives a new wire
+                               //   called "<cell>.abc9_ff.Q" that is used below
+                               if (box_module->get_bool_attribute("\\abc9_flop")) {
                                        box_inputs++;
-                                       holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
+                                       Wire *holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
                                        if (!holes_wire) {
                                                holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
                                                holes_wire->port_input = true;
@@@ -1059,13 -844,12 +1057,17 @@@ struct Abc9OpsPass : public Pass 
                }
                extra_args(args, argidx, design);
  
-               // TODO: Check at least one mode given
 -              if (!(break_scc_mode || unbreak_scc_mode || prep_dff_mode || reintegrate_mode))
 -                      log_cmd_error("At least one of -{,un}break_scc, -prep_{dff,holes}, -reintegrate must be specified.\n");
++              if (!(check_mode || break_scc_mode || unbreak_scc_mode || prep_times_mode || prep_holes_mode || prep_dff_mode || !write_box_src.empty() || reintegrate_mode))
++                      log_cmd_error("At least one of -check, -{,un}break_scc, -prep_{times,holes,dff}, -write_box, -reintegrate must be specified.\n");
+ 
+               if (dff_mode && !prep_holes_mode)
+                       log_cmd_error("'-dff' option is only relevant for -prep_holes.\n");
  
 +              if (check_mode)
 +                      check(design);
 +              if (prep_times_mode)
 +                      prep_times(design);
 +
                for (auto mod : design->selected_modules()) {
                        if (mod->get_bool_attribute("\\abc9_holes"))
                                continue;