(no commit message)

diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index a477028f5e1c3ce798fc9dd2531d8623dcb97e65..deb8e0ff1487d4b2e9f88514265d4448a1cfe383 100644 (file)
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -14,12 +14,15 @@ Links:
 * [[openpower/isa/comparefixed]]
 
 Condition Register Fields are only 4 bits wide: this presents some
-interesting conceptual challenges for SVP64, particularly with respect to element
-width (which is clearly meaningless for a 4-bit
-collation of Conditions, EQ LT GE SO). Likewise, arithmetic saturation
+interesting conceptual challenges for SVP64, which was designed
+primarily for vectors of arithmetic and logical operations. However
+if predicates may be bits of CR Fields it makes sense to extend
+SVP64 to cover CR Operations.
+
+Element width however is clearly meaningless for a 4-bit
+collation of Conditions, EQ LT GE SO. Likewise, arithmetic saturation
 (an important part of Arithmetic SVP64)
-has no meaning. Additionally, extra modes are required that only make
-sense for Vectorised CR Operations. Consequently an alternative Mode Format is required, and given that elwidths are meaningless for CR Fields
+has no meaning. An alternative Mode Format is required, and given that elwidths are meaningless for CR Fields
 the bits in SVP64 `RM` may be used for other purposes.
 
 This alternative mapping **only** applies to instructions that **only**