ARM: Add a version of the Dest and Op1 operands for accessing the MiscRegs.

diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index e2b73e2e2966c2aacdbb992f79c84e6b48a56471..903982f2904ba22b5f9ecf7c8e9920d63dd69a87 100644 (file)
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -94,12 +94,14 @@ def operands {{
                maybePCRead, maybeIWPCWrite),
     'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 0,
                 maybePCRead, maybeAIWPCWrite),
+    'MiscDest': ('ControlReg', 'uw', 'dest', (None, None, 'IsControl'), 0),
     'Base': ('IntReg', 'uw', 'base', 'IsInteger', 1,
              maybeAlignedPCRead, maybePCWrite),
     'Index': ('IntReg', 'uw', 'index', 'IsInteger', 2,
               maybePCRead, maybePCWrite),
     'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 3,
               maybePCRead, maybePCWrite),
+    'MiscOp1': ('ControlReg', 'uw', 'op1', (None, None, 'IsControl'), 0),
     'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 4,
               maybePCRead, maybePCWrite),
     'Op3': ('IntReg', 'uw', 'op3', 'IsInteger', 4,