(no commit message)

diff --git a/openpower/sv/int_fp_mv.mdwn b/openpower/sv/int_fp_mv.mdwn
index c3e31c8f6ea2109d88f92935016eec4e6c70b5ab..397afdc7a3435a303ba3952be7c7807943ed0749 100644 (file)
--- a/openpower/sv/int_fp_mv.mdwn
+++ b/openpower/sv/int_fp_mv.mdwn
@@ -113,12 +113,12 @@ These are like a variant of `fmvfg` and `oris`, combined.
 Power ISA currently requires a large
 number of instructions to get Floating Point constants into registers.
 `fmvis` on its own is equivalent to BF16 to FP32/64 conversion,
-but if followed up by `frlsi` an additional 16 bits of accuracy in the
+but if followed up by `fishmv` an additional 16 bits of accuracy in the
 mantissa may be achieved.
 
 *IBM may consider it worthwhile to extend these two instructions to
-v3.1 Prefixed (`pfmvis` and `pfrlsi`). If so it is recommended that
-`pfmvis` load a full FP32 immediate and `pfrlsi` supplies the three high
+v3.1 Prefixed (`pfmvis` and `pfishmv`). If so it is recommended that
+`pfmvis` load a full FP32 immediate and `pfishmv` supplies the three high
 missing exponent bits (numbered 8 to 10) and the lower additional
 29 mantissa bits (23 to 51) needed to construct a full FP64 immediate.*