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add SV VLIW idea
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 19 Jun 2019 14:59:57 +0000 (15:59 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 19 Jun 2019 14:59:57 +0000 (15:59 +0100)
simple_v_extension/specification.mdwn patch | blob | history

diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn
index 8f6c98bf1bd257655a693592ed9722a972b76ce9..3d0838a78d9a6e5d6328d97906d5e30d5f778713 100644 (file)
--- a/simple_v_extension/specification.mdwn
+++ b/simple_v_extension/specification.mdwn
@@ -2230,8 +2230,9 @@ Optional VL/MAXVL/SubVL Block:
 
 Reminder of the variable-length format from Section 1.5 of the RISC-V ISA:
 
-| .. | xxxx | xxxxxxxxxxxxxxxx | xnnnxxxxx1111111 | (80+16\*nnn)-bit, nnn!=111 |
-| -- | ---- | ---------------- | ---------------- | -------------------------- |
+| base+4 | base+2           | base             | number of bits             |
+| ------ | ---------------- | ---------------- | -------------------------- |
+| ..xxxx | xxxxxxxxxxxxxxxx | xnnnxxxxx1111111 | (80+16\*nnn)-bit, nnn!=111 |
 
 Notes:
 
http://libre-riscv.org ikiwiki