freedreno/a5xx: enable a540

Tested-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com>
Signed-off-by: Rob Clark <robdclark@chromium.org>

diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_emit.c b/src/gallium/drivers/freedreno/a5xx/fd5_emit.c
index bdf590a7e3c7adcf51259eafb6d6fb341b8f1906..146a2951ff6e95b2d031580e4d68380bcad33172 100644 (file)
--- a/src/gallium/drivers/freedreno/a5xx/fd5_emit.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_emit.c
@@ -919,8 +919,19 @@ t7              opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
        OUT_PKT4(ring, REG_A5XX_SP_MODE_CNTL, 1);
        OUT_RING(ring, 0x0000001e);   /* SP_MODE_CNTL */
 
-       OUT_PKT4(ring, REG_A5XX_SP_DBG_ECO_CNTL, 1);
-       OUT_RING(ring, 0x40000800);   /* SP_DBG_ECO_CNTL */
+       if (ctx->screen->gpu_id == 540) {
+               OUT_PKT4(ring, REG_A5XX_SP_DBG_ECO_CNTL, 1);
+               OUT_RING(ring, 0x800);   /* SP_DBG_ECO_CNTL */
+
+               OUT_PKT4(ring, REG_A5XX_HLSQ_DBG_ECO_CNTL, 1);
+               OUT_RING(ring, 0x0);
+
+               OUT_PKT4(ring, REG_A5XX_VPC_DBG_ECO_CNTL, 1);
+               OUT_RING(ring, 0x800400);
+       } else {
+               OUT_PKT4(ring, REG_A5XX_SP_DBG_ECO_CNTL, 1);
+               OUT_RING(ring, 0x40000800);   /* SP_DBG_ECO_CNTL */
+       }
 
        OUT_PKT4(ring, REG_A5XX_TPL1_MODE_CNTL, 1);
        OUT_RING(ring, 0x00000544);   /* TPL1_MODE_CNTL */

diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c b/src/gallium/drivers/freedreno/freedreno_screen.c
index 820b4468a8ce440fad1d676ae3d750fd5cabee1c..6c3e8a000a70df12c6a0bbf24e4c90e2899dda89 100644 (file)
--- a/src/gallium/drivers/freedreno/freedreno_screen.c
+++ b/src/gallium/drivers/freedreno/freedreno_screen.c
@@ -880,6 +880,7 @@ fd_screen_create(struct fd_device *dev, struct renderonly *ro)
                fd4_screen_init(pscreen);
                break;
        case 530:
+       case 540:
                fd5_screen_init(pscreen);
                break;
        case 630: