According to the gas manual, +simd implies +fp and +crypto implies +simd.
Make sure +nofp turns +simd, +crypto and +fp16 off.
gas/
2016-11-07 Szabolcs Nagy <szabolcs.nagy@arm.com>
* config/tc-aarch64.c (aarch64_features): Fix "simd" and "crypto".
* testsuite/gas/aarch64/illegal-crypto-nofp.d: New.
* testsuite/gas/aarch64/illegal-crypto-nofp.l: New.
* testsuite/gas/aarch64/illegal-fp16-nofp.d: New.
* testsuite/gas/aarch64/illegal-fp16-nofp.l: New.
* testsuite/gas/aarch64/illegal-fp16-nofp.s: New.
+2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
+
+ * config/tc-aarch64.c (aarch64_features): Fix "simd" and "crypto".
+ * testsuite/gas/aarch64/illegal-crypto-nofp.d: New.
+ * testsuite/gas/aarch64/illegal-crypto-nofp.l: New.
+ * testsuite/gas/aarch64/illegal-fp16-nofp.d: New.
+ * testsuite/gas/aarch64/illegal-fp16-nofp.l: New.
+ * testsuite/gas/aarch64/illegal-fp16-nofp.s: New.
+
2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
PR binutils/20799
{"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC, 0),
AARCH64_ARCH_NONE},
{"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO, 0),
- AARCH64_ARCH_NONE},
+ AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0)},
{"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP, 0),
AARCH64_ARCH_NONE},
{"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE, 0),
AARCH64_ARCH_NONE},
{"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0),
- AARCH64_ARCH_NONE},
+ AARCH64_FEATURE (AARCH64_FEATURE_FP, 0)},
{"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN, 0),
AARCH64_ARCH_NONE},
{"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR, 0),
--- /dev/null
+#as: -march=armv8-a+crypto+nofp
+#source: crypto.s
+#error-output: illegal-crypto-nofp.l
--- /dev/null
+[^:]*: Assembler messages:
+[^:]+:27: Error: selected processor does not support `aese v7\.16b,v31\.16b'
+[^:]+:28: Error: selected processor does not support `aesd v7\.16b,v31\.16b'
+[^:]+:29: Error: selected processor does not support `aesmc v7\.16b,v31\.16b'
+[^:]+:30: Error: selected processor does not support `aesimc v7\.16b,v31\.16b'
+[^:]+:32: Error: selected processor does not support `sha1h s7,s31'
+[^:]+:33: Error: selected processor does not support `sha1su1 v7\.4s,v31\.4s'
+[^:]+:34: Error: selected processor does not support `sha256su0 v7\.4s,v31\.4s'
+[^:]+:36: Error: selected processor does not support `sha1c q7,s15,v31\.4s'
+[^:]+:37: Error: selected processor does not support `sha1p q7,s15,v31\.4s'
+[^:]+:38: Error: selected processor does not support `sha1m q7,s15,v31\.4s'
+[^:]+:40: Error: selected processor does not support `sha1su0 v7\.4s,v15\.4s,v31\.4s'
+[^:]+:41: Error: selected processor does not support `sha256h q7,q15,v31\.4s'
+[^:]+:42: Error: selected processor does not support `sha256h2 q7,q15,v31\.4s'
+[^:]+:43: Error: selected processor does not support `sha256su1 v7\.4s,v15\.4s,v31\.4s'
+[^:]+:45: Error: selected processor does not support `pmull v7\.8h,v15\.8b,v31\.8b'
+[^:]+:46: Error: selected processor does not support `pmull v7\.1q,v15\.1d,v31\.1d'
+[^:]+:47: Error: selected processor does not support `pmull2 v7\.8h,v15\.16b,v31\.16b'
+[^:]+:48: Error: selected processor does not support `pmull2 v7\.1q,v15\.2d,v31\.2d'
--- /dev/null
+#as: -march=armv8.2-a+fp16+nofp -mno-verbose-error
+#error-output: illegal-fp16-nofp.l
--- /dev/null
+[^:]*: Assembler messages:
+[^:]+:3: Error: selected processor does not support `fneg s0,s1'
+[^:]+:4: Error: selected processor does not support `fneg h0,h1'
+[^:]+:5: Error: selected processor does not support `fneg v0\.4s,v1\.4s'
+[^:]+:6: Error: selected processor does not support `fneg v0\.8h,v1\.8h'
+[^:]+:7: Error: selected processor does not support `neg v0\.16b,v1\.16b'
--- /dev/null
+// Test -march=armv8.2-a+fp16+nofp to disable fp, fp16 and simd.
+.text
+ fneg s0, s1
+ fneg h0, h1
+ fneg v0.4s, v1.4s
+ fneg v0.8h, v1.8h
+ neg v0.16b, v1.16b