i965: Make brw_texture_offset() not use ir_texture.

Our new IR won't have ir_texture objects.

Signed-off-by: Connor Abbott <connor.abbott@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>

diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 45c7570b3aca329c5581e8303a468ae47d6f1612..ad348f7e0cfdae0d1232780691ce0fcfd4552274 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -1944,7 +1944,9 @@ fs_visitor::visit(ir_texture *ir)
           * use offset_value.file to distinguish between no offset, a constant
           * offset, and a non-constant offset.
           */
-         offset_value = fs_reg(brw_texture_offset(ctx, const_offset));
+         offset_value =
+            fs_reg(brw_texture_offset(ctx, const_offset->value.i,
+                                      const_offset->type->vector_elements));
       } else {
          ir->offset->accept(this);
          offset_value = this->result;

diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp
index 6e17beb16c4f7b6002370939f19b6603d8a10ddc..cd1e7eb699eadbc3fb5b959c33d59c58a6b7773f 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -358,18 +358,15 @@ brw_math_function(enum opcode op)
 }
 
 uint32_t
-brw_texture_offset(struct gl_context *ctx, ir_constant *offset)
+brw_texture_offset(struct gl_context *ctx, int *offsets,
+                   unsigned num_components)
 {
    /* If the driver does not support GL_ARB_gpu_shader5, the offset
     * must be constant.
     */
-   assert(offset != NULL || ctx->Extensions.ARB_gpu_shader5);
+   assert(offsets != NULL || ctx->Extensions.ARB_gpu_shader5);
 
-   if (!offset) return 0;  /* nonconstant offset; caller will handle it. */
-
-   signed char offsets[3];
-   for (unsigned i = 0; i < offset->type->vector_elements; i++)
-      offsets[i] = (signed char) offset->value.i[i];
+   if (!offsets) return 0;  /* nonconstant offset; caller will handle it. */
 
    /* Combine all three offsets into a single unsigned dword:
     *
@@ -378,7 +375,7 @@ brw_texture_offset(struct gl_context *ctx, ir_constant *offset)
     *    bits  3:0 - R Offset (Z component)
     */
    unsigned offset_bits = 0;
-   for (unsigned i = 0; i < offset->type->vector_elements; i++) {
+   for (unsigned i = 0; i < num_components; i++) {
       const unsigned shift = 4 * (2 - i);
       offset_bits |= (offsets[i] << shift) & (0xF << shift);
    }

diff --git a/src/mesa/drivers/dri/i965/brw_shader.h b/src/mesa/drivers/dri/i965/brw_shader.h
index f0d4f857cf1a52ddd75a23de212c66dc906e2d8c..94db98702b9f32e4282f425e0eda806f1e1b61ca 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_shader.h
+++ b/src/mesa/drivers/dri/i965/brw_shader.h
@@ -182,7 +182,8 @@ public:
    virtual void invalidate_live_intervals() = 0;
 };
 
-uint32_t brw_texture_offset(struct gl_context *ctx, ir_constant *offset);
+uint32_t brw_texture_offset(struct gl_context *ctx, int *offsets,
+                            unsigned num_components);
 
 #endif /* __cplusplus */
 

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 88ec79e98f1a5936719fc9a58fb4af29201a4639..8e32d8b92d1da4dd994284a87d2bd68c3e3ac0a5 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -2552,8 +2552,11 @@ vec4_visitor::visit(ir_texture *ir)
 
    vec4_instruction *inst = new(mem_ctx) vec4_instruction(this, opcode);
 
-   if (ir->offset != NULL)
-      inst->texture_offset = brw_texture_offset(ctx, ir->offset->as_constant());
+   if (ir->offset != NULL && !has_nonconstant_offset) {
+      inst->texture_offset =
+         brw_texture_offset(ctx, ir->offset->as_constant()->value.i,
+                            ir->offset->type->vector_elements);
+   }
 
    /* Stuff the channel select bits in the top of the texture offset */
    if (ir->op == ir_tg4)