ecp5: Compatibility with Migen AsyncResetSynchronizer

Signed-off-by: David Shah <davey1576@gmail.com>

diff --git a/techlibs/ecp5/cells_map.v b/techlibs/ecp5/cells_map.v
index 23182bdebe5091cb2aeac665514a3fd3f4f353c2..6ab4b69f2af19762f7a566ce5d45ad8be3b5d9f9 100644 (file)
--- a/techlibs/ecp5/cells_map.v
+++ b/techlibs/ecp5/cells_map.v
@@ -47,6 +47,9 @@ module  \$__DFFSE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"
 module  \$__DFFSE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
 module  \$__DFFSE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
 
+// For Diamond compatibility, FIXME: add all Diamond flipflop mappings
+module FD1S3BX(input PD, D, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .DI(D), .Q(Q)); endmodule
+
 `ifndef NO_LUT
 module \$lut (A, Y);
     parameter WIDTH = 0;

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index ca5d020f38279854573110dbbbd52ba5c6908d02..d2d8b57934f7a23b5a00f9f072c6c43e7c3fdf98 100644 (file)
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -556,3 +556,20 @@ module DP16KD(
   parameter INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
   parameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 endmodule
+
+// For Diamond compatibility, FIXME: add all Diamond flipflop mappings
+module FD1S3BX(input PD, D, CK, output Q);
+       TRELLIS_FF #(
+               .GSR("DISABLED"),
+               .CEMUX("1"),
+               .CLKMUX("CLK"),
+               .LSRMUX("LSR"),
+               .REGSET("SET"),
+               .SRMODE("ASYNC")
+       ) tff_i (
+               .CLK(CK),
+               .LSR(PD),
+               .DI(D),
+               .Q(Q)
+       );
+endmodule